PCI4451 datasheet(46/216 Pages) TI

46 / 216 page

3–2

Tied for Open Drain

Pad

VCCP

Figure 3–2. 3-State Bidirectional Buffer

3.2

Clamping Voltages

The I/O sites can be pulled through a clamping diode to a voltage rail for protection. The 3.3-V core power supply

is independent of the clamping voltages. The clamping (protection) diodes are required if the signaling environment

on an I/O is system dependent. For example, PCI signaling can be either 3.3 Vdc or 5.0 Vdc, and the PCI4451 must

reliably accommodate both voltage levels. This is accomplished by using a 3.3-V buffer with a clamping diode to VCCP.

If a system design requires a 5.0-V PCI bus, then VCCP must be connected to the 5.0-V power supply.

A standard die has only one clamping voltage for the sites as shown in Figure 3–2. After the terminal assignments

are fixed, the fabrication facility will support a design by splitting the clamping voltage for customization. The PCI4451

requires five separate clamping voltages since it supports a wide range of features. The five voltages are listed and

defined in Section 12.2, Recommended Operating Conditions.

3.3

Peripheral Component Interconnect (PCI) Interface

This section describes the PCI interface of the PCI4451, and how the device responds to and participates in PCI bus

cycles. The PCI4451 provides all required signals for PCI master/slave devices and may operate in either 5-V or 3.3-V

PCI signaling environments by connecting the VCCP terminals to the desired signaling level.

3.3.1

PCI Bus Lock (LOCK)

The bus locking protocol defined in the PCI Specification is not highly recommended, but is provided on the PCI4451

as an additional compatibility feature. The PCI LOCK terminal is multiplexed with GPIO2, and the terminal function

defaults to a general-purpose input (GPI). The use of LOCK is only supported by PCI-to-CardBus bridges in the

downstream direction (away from the processor).

PCI LOCK indicates an atomic operation that may require multiple transactions to complete. When LOCK is asserted,

nonexclusive transactions may proceed to an address that is not currently locked. A grant to start a transaction on

the PCI bus does not guarantee control of LOCK; control of LOCK is obtained under its own protocol. It is possible

for different initiators to use the PCI bus while a single master retains ownership of LOCK. To avoid confusion with

the PCI bus clock, the CardBus signal for this protocol is CBLOCK.

An agent may need to do an exclusive operation because a critical memory access to memory might be broken into

several transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock is defined

by PCI to be 16 bytes aligned. The lock protocol defined by PCI allows a resource lock without interfering with

nonexclusive, real-time data transfer, such as video.

The PCI bus arbiter may be designed to support only complete bus locks using the LOCK protocol. In this scenario

the arbiter will not grant the bus to any other agent (other than the LOCK master) while LOCK is asserted. A complete

bus lock may have a significant impact on the performance of the video. The arbiter that supports complete bus lock

must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked operation

is in progress.

The PCI4451 supports all LOCK protocol associated with PCI-to-PCI bridges, as also defined for PCI-to-CardBus

bridges. This includes disabling write posting while a locked operation is in progress, which can solve a potential

deadlock when using devices such as PCI-to-PCI bridges. The potential deadlock can occur if a CardBus target

PCI4451 Datasheet(PDF) 46 Page - Texas Instruments

PCI4451 Datasheet(HTML) 46 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL