PCI4451 datasheet(63/216 Pages) TI

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3.6

Power Management Overview

In addition to the low-power CMOS technology process used for the PCI4451, various features are designed into the

device to allow implementation of popular power saving techniques. These features and techniques are discussed

in this section.

3.6.1

CLKRUN Protocol

CLKRUN is the primary method of power management on the PCI bus side of the PCI4451. Since some chipsets

do not implement CLKRUN, this is not always available to the system designer, and alternate power savings features

are provided.

If CLKRUN is not implemented, then the CLKRUN terminal should be tied low. CLKRUN is enabled by default via bit

1 (KEEPCLK) in the system control register (PCI offset 80h, see Section 4.28).

3.6.2

CardBus PC Card Power Management

The PCI4451 implements its own card power management engine that can turn off the CCLK to a socket when there

is no activity to the CardBus PC Card. The CCLK speed can also be divided by 16 rather than stopped. The CLKRUN

protocol is followed on the CardBus interface to control this clock management.

3.6.3

PCI Bus Power Management

The PCI Bus Power Management Interface Specification (PCIPM) establishes the infrastructure required to let the

operating system control the power of PCI functions. This is done by defining a standard PCI interface and operations

to manage the power of PCI functions on the bus. The PCI bus and the PCI functions can be assigned one of four

software visible power management states, which result in varying levels of power savings.

The four power management states of PCI functions are: D0 — fully on state, D1 and D2 — intermediate states, and

D3 — off state. Similarly, bus power states of the PCI bus are B0–B3. The bus power states B0–B3 are derived from

the device power state of the upstream bridge device.

For the operating system to manage the device power states on the PCI bus, the PCI function should support four

power management operations. The four operations are: capabilities reporting; power status reporting; setting the

power state; and system wake-up. The operating system identifies the capabilities of the PCI function by traversing

the new capabilities list. The presence of new capabilities is indicated by a 1b in bit 4 of the PCI status register (PCI

offset 06h, see Section 4.5). When software determines that the device has a capabilities list by seeing that bit 4 of

the PCI status register is set, it will read the capability pointer register (PCI offset 14h, see Section 4.12). This value

in the register points to the location in PCI configuration space of the capabilities linked list.

The first byte of each capability register block is required to be a unique ID of that capability. PCI power management

has been assigned an ID of 01h. The next byte is a pointer to the next pointer item in the list of capabilities. If there

are no more items in the list, then the next item pointer should be set to 0. The registers following the next item pointer

are specific to the function’s capability. The PCIPM capability implements the following register block:

Power Management Register Block

Power management capabilities (PMC)

Next item pointer

Capability ID

Offset = 0

Data

PMCSR bridge support extensions

Power management control status (CSR)

Offset = 4

The power management capabilities (PMC) register is a static read-only register that provides information on the

capabilities of the function, related to power management. The PMCSR register enables control of power

management states and enables/monitors power management events. The data register is an optional register that

provides a mechanism for state-dependent power measurements such as power consumed or heat dissipation.

3.6.4

CardBus Device Class Power Management

The PCI Bus Interface Specification for PCI-to-CardBus Bridges was approved by PCMCIA in December of 1997.

This specification follows the device and bus state definitions provided in the PCI Bus Power Management Interface

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