PCI4451 datasheet(76/216 Pages) TI

76 / 216 page

4–8

4.13 Secondary Status Register

The secondary status register is compatible with the PCI-PCI bridge secondary status register. It indicates CardBus

related device information to the host system. This register is very similar to the PCI status register (offset 06h), and

status bits are cleared by a writing a 1. This register is not shared by the two socket functions, but is accessed on

a per socket basis. See Table 4–4 for a complete description of the register contents.

Bit

Name

Secondary status

Type

Default

Secondary status

Type:

Read-only, Read/2Clear

Offset:

16h

Default:

0200h

Table 4–4. Secondary Status Register Description

BIT

SIGNAL

TYPE

FUNCTION

CBPARITY

Detected parity error. This bit is set when a CardBus parity error is detected, either address or data parity

errors. Write a 1 to clear this bit.

CBSERR

Signaled system error. This bit is set when CSERR is signaled by a CardBus card. The PCI4451 does not

assert the CSERR signal. Write a 1 to clear this bit.

CBMABORT

Received master abort. This bit is set when a cycle initiated by the PCI4451 on the CardBus bus has been

terminated by a master abort. Write a 1 to clear this bit.

REC_CBTA

Received target abort. This bit is set when a cycle initiated by the PCI4451 on the CardBus bus was

terminated by a target abort. Write a 1 to clear this bit.

SIG_CBTA

Signaled target abort. This bit is set by the PCI4451 when it terminates a transaction on the CardBus bus

with a target abort. Write a 1 to clear this bit.

10–9

CB_SPEED

CDEVSEL timing. These bits encode the timing of CDEVSEL and are hardwired to 01b indicating that the

PCI4451 asserts this signal at a medium speed.

CB_DPAR

CardBus data parity error detected. Write a 1 to clear this bit.

0 = The conditions for setting this bit have not been met.

1 = A data parity error occurred and the following conditions were met:

a. CPERR was asserted on the CardBus interface.

b. The PCI4451 was the bus master during the data parity error.

c. The parity error response enable bit (bit 0) is set in the bridge control register (offset 3Eh, see

Section 4.24).

CBFBB_CAP

Fast back-to-back capable. The PCI4451 cannot accept fast back-to-back transactions; therefore, this bit

is hardwired to 0.

CB_UDF

User definable feature support. The PCI4451 does not support the user definable features; therefore, this

bit is hardwired to 0.

CB66MHZ

66-MHz capable. The PCI4451 CardBus interface operates at a maximum CCLK frequency of 33 MHz;

therefore, this bit is hardwired to 0.

4–0

RSVD

These bits return 0s when read.

PCI4451 Datasheet(PDF) 76 Page - Texas Instruments

PCI4451 Datasheet(HTML) 76 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL