PCI4451 datasheet(71/216 Pages) TI

71 / 216 page

4–3

4.4

PCI Command Register

The command register provides control over the PCI4451 interface to the PCI bus. All bit functions adhere to the

definitions in the PCI Local Bus Specification, see Table 4–2. None of the bit functions in this register are shared

between the two PCI4451 PCI functions. Two command registers exist in the PCI4451, one for each function.

Software manipulates the two PCI4451 functions as separate entities when enabling functionality through the

command register. The SERR_EN and PERR_EN enable bits in this register are internally wired OR between the

two functions, and these control bits appear separate per function to software.

Bit

Name

PCI command

Type

R/W

Default

PCI command

Type:

Read-only, Read/Write

Offset:

04h

Default:

0000h

Table 4–2. PCI Command Register Description

BIT

SIGNAL

TYPE

FUNCTION

15–10

RSVD

Bits 15–10 return 0s when read.

FBB_EN

Fast back-to-back enable. The PCI4451 will not generate fast back-to-back transactions; therefore, this bit

is read-only. This bit returns a 0 when read.

SERR_EN

R/W

System error (SERR) enable. This bit controls the enable for the SERR driver on the PCI interface. SERR

can be asserted after detecting an address parity error on the PCI bus. Both this bit and bit 6 must be set

for the PCI4451 to report address parity errors.

0 = Disables the SERR output driver (default)

1 = Enables the SERR output driver

STEP_EN

Address/data stepping control. The PCI4451 does not support address/data stepping, and this bit is

hardwired to 0. Writes to this bit have no effect.

PERR_EN

R/W

Parity error response enable. This bit controls the PCI4451 response to parity errors through the PERR

signal. Data parity errors are indicated by asserting PERR, while address parity errors are indicated by

asserting SERR.

0 = PCI4451 ignores detected parity error (default).

1 = PCI4451 responds to detected parity errors.

VGA_EN

R/W

VGA palette snoop. When set to 1, palette snooping is enabled (i.e., the PCI4451 does not respond to palette

other accesses.

MWI_EN

Memory write and invalidate enable. This bit controls whether a PCI initiator device can generate memory

write-and-invalidate commands. The PCI4451 controller does not support memory write-and-invalidate

commands, it uses memory write commands instead; therefore, this bit is hardwired to 0. This bit returns

0 when read. Writes to this bit have no effect.

SPECIAL

Special cycles. This bit controls whether or not a PCI device ignores PCI special cycles. The PCI4451 does

not respond to special cycle operations; therefore, this bit is hardwired to 0. This bit returns 0 when read.

Writes to this bit have no effect.

MAST_EN

R/W

Bus master control. This bit controls whether or not the PCI4451 can act as a PCI bus initiator (master). The

PCI4451 can take control of the PCI bus only when this bit is set.

0 = Disables the PCI4451 ability to generate PCI bus accesses (default)

1 = Enables the PCI4451 ability to generate PCI bus accesses

MEM_EN

R/W

Memory space enable. This bit controls whether or not the PCI4451 may claim cycles in PCI memory space.

0 = Disables the PCI4451 response to memory space accesses (default)

1 = Enables the PCI4451 response to memory space accesses

IO_EN

R/W

I/O space control. This bit controls whether or not the PCI4451 may claim cycles in PCI I/O space.

0 = Disables the PCI4451 from responding to I/O space accesses (default)

1 = Enables the PCI4451 to respond to I/O space accesses

PCI4451 Datasheet(PDF) 71 Page - Texas Instruments

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