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PCI4451 Datasheet(PDF) 33 Page - Texas Instruments |
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PCI4451 Datasheet(HTML) 33 Page - Texas Instruments |
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33 / 216 page  2–15 Table 2–10. PCI Address and Data Terminals TERMINAL I/O FUNCTION NAME GFN NO. GJG NO. I/O FUNCTION AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 L18 L19 M20 M19 M18 M17 N20 N19 P18 R20 R19 P17 R18 T20 T19 T18 Y19 W18 V17 U16 Y18 W17 V16 Y17 V15 U14 Y16 W15 Y15 W14 Y14 V13 L15 L18 L19 L16 M15 M16 M18 M19 N15 N14 P18 P19 P16 R18 R19 R15 W17 V16 W16 T15 V15 W15 P14 R14 W14 P13 R13 T13 N13 R12 T12 V12 I/O PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary interface. During the address phase of a primary bus PCI cycle, AD31–AD0 contain a 32-bit address or other destination information. During the data phase, AD31–AD0 contain data. C/BE3 C/BE2 C/BE1 C/BE0 N18 U20 V18 W16 M14 R16 T16 T14 I/O PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the address phase of a primary bus PCI cycle, C/BE3–C/BE0 define the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. C/BE0 applies to byte 0 (AD7–AD0), C/BE1 applies to byte 1 (AD15–AD8), C/BE2 applies to byte 2 (AD23–AD16), and C/BE3 applies to byte 3 (AD31–AD24). PAR W19 V17 I/O PCI bus parity. In all PCI bus read and write cycles, the PCI4451 calculates even parity across the AD31–AD0 and C/BE3–C/BE0 buses. As an initiator during PCI cycles, the PCI4451 outputs this parity indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is compared to the initiator’s parity indicator. A compare error results in the assertion of a parity error (PERR). |
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