PCI4451 datasheet(7/216 Pages) TI

7 / 216 page

vii

9.11

Global Unique ID Low Register

9–10

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.12

Configuration ROM Mapping Register

9–11

. . . . . . . . . . . . . . . . . . . . . . . . . .

9.13

Posted Write Address Low Register

9–11

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.14

Posted Write Address High Register

9–12

. . . . . . . . . . . . . . . . . . . . . . . . . . .

9.15

Vendor ID Register

9–12

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.16

Host Controller Control Register

9–13

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.17

Self ID Buffer Pointer Register

9–14

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.18

Self ID Count Register

9–14

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.19

Isochronous Receive Channel Mask High Register

9–15

. . . . . . . . . . . . . .

9.20

Isochronous Receive Channel Mask Low Register

9–16

. . . . . . . . . . . . . . .

9.21

Interrupt Event Register

9–17

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.22

Interrupt Mask Register

9–18

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.23

Isochronous Transmit Interrupt Event Register

9–19

. . . . . . . . . . . . . . . . . .

9.24

Isochronous Transmit Interrupt Mask Register

9–20

. . . . . . . . . . . . . . . . . . .

9.25

Isochronous Receive Interrupt Event Register

9–20

. . . . . . . . . . . . . . . . . . .

9.26

Isochronous Receive Interrupt Mask Register

9–21

. . . . . . . . . . . . . . . . . . .

9.27

Fairness Control Register (Optional Register)

9–21

. . . . . . . . . . . . . . . . . . .

9.28

Link Control Register

9–22

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.29

Node Identification Register

9–23

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.30

PHY Control Register

9–24

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.31

Isochronous Cycle Timer Register

9–25

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.32

Asynchronous Request Filter High Register

9–26

. . . . . . . . . . . . . . . . . . . . .

9.33

Asynchronous Request Filter Low Register

9–28

. . . . . . . . . . . . . . . . . . . . .

9.34

Physical Request Filter High Register

9–29

. . . . . . . . . . . . . . . . . . . . . . . . . .

9.35

Physical Request Filter Low Register

9–31

. . . . . . . . . . . . . . . . . . . . . . . . . .

9.36

Physical Upper Bound Register (Optional Register)

9–31

. . . . . . . . . . . . . .

9.37

Asynchronous Context Control Register

9–32

. . . . . . . . . . . . . . . . . . . . . . . .

9.38

Asynchronous Context Command Pointer Register

9–33

. . . . . . . . . . . . . .

9.39

Isochronous Transmit Context Control Register

9–34

. . . . . . . . . . . . . . . . . .

9.40

Isochronous Transmit Context Command Pointer Register

9–35

. . . . . . . .

9.41

Isochronous Receive Context Control Register

9–36

. . . . . . . . . . . . . . . . . .

9.42

Isochronous Receive Context Command Pointer Register

9–37

. . . . . . . .

9.43

Isochronous Receive Context Match Register

9–38

. . . . . . . . . . . . . . . . . . .

10 GPIO Interface

10–1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11 Serial EEPROM

11–1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.1

Serial Bus Interface

11–1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12 Electrical Characteristics

12–1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.1

Absolute Maximum Ratings Over Operating Temperature Ranges

12–1

12.2

Recommended Operating Conditions

12–2

. . . . . . . . . . . . . . . . . . . . . . . . . .

12.3

Electrical Characteristics Over Recommended Operating Conditions 12–3

12.4

PCI Clock/Reset Timing Requirements Over Recommended Ranges

of Supply Voltage and Operating Free-Air Temperature

12–4

. . . . . . . . . .

12.5

PCI Timing Requirements Over Recommended Ranges of Supply

Voltage and Operating Free-Air Temperature

12–4

. . . . . . . . . . . . . . . . . . .

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