PCI4451 datasheet(32/216 Pages) TI

32 / 216 page

2–14

The terminals are grouped in tables by functionality such as PCI system function, power supply function, etc., for quick

reference (see Table 2–7 through Table 2–21). The terminal names and numbers are also listed for convenient

reference.

Table 2–7. Power Supply Terminals

TERMINAL

FUNCTION

NAME

GFN NO.

GJG NO.

FUNCTION

GND

A1, D4, D8, D13, D17, H4, H17,

N4, N17, U4, U8, U13, U17

A3, A16, C1, D8, F12, G1,

G19, M2, N16, T4, T7, V14,

W12

Device ground terminals

VCC

D6, D11, D15, F4, F17, K4, L17,

R4, R17, U6, U10, U15

A11, D14, E1, E6, E19, J14,

P1, P15, T5, V10, V13

Power supply terminal for core logic (3.3 Vdc)

VCCA

B5, F3, L4

B6, F1, K5

Clamp voltage for PC Card A interface. Indicates Card A

signaling environment.

VCCB

B13, E19

B12, F18

Clamp voltage for PC Card B interface. Indicates Card B

signaling environment.

VCCP

P19, V14

N18, W13

Clamp voltage for PCI signaling (3.3 Vdc or 5 Vdc)

Table 2–8. PC Card Power Switch Terminals

TERMINAL

I/O

FUNCTION

NAME

GFN NO.

GJG NO.

I/O

FUNCTION

CLOCK

U12

T11

I/O

3-line power switch clock. Information on the DATA line is sampled at the rising edge of

CLOCK. This terminal defaults as an input which means an external clock source must

be used. If the internal ring oscillator is used, then an external CLOCK source is not

required. The internal oscillator may be enabled by setting bit 27 (P2CCLK) of the system

control register (PCI offset 80h, see Section 4.28) to a 1b.

A 43 k

W pulldown resistor should be tied to this terminal.

DATA

V12

V11

3-line power switch data. DATA is used to serially communicate socket power-control

information to the power switch.

LATCH

W12

W11

3-line power switch latch. LATCH is asserted by the PCI4451 to indicate to the PC Card

power switch that the data on the DATA line is valid.

Table 2–9. PCI System Terminals

TERMINAL

I/O

FUNCTION

NAME

GFN NO.

GJG NO.

I/O

FUNCTION

CLKRUN

K18

I/O

PCI clock run. CLKRUN is used by the central resource to request permission to stop the

PCI clock or to slow it down, and the PCI4451 responds accordingly. If CLKRUN is not

implemented, then this terminal should be tied low. CLKRUN is enabled by default by bit 1

(KEEPCLK) in the system control register (PCI offset 80h, see Section 4.28).

PCLK

K17

K15

PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are

sampled at the rising edge of PCLK.

PRST

K19

PCI bus reset. When the PCI bus reset is asserted, PRST causes the PCI4451 to place all

output buffers in a high-impedance state and reset all internal registers. When PRST is

asserted, the device is completely nonfunctional. After PRST is deasserted, the PCI4451 is

in its default state. When the SUSPEND mode is enabled, the device is protected from the

PRST and the internal registers are preserved. All outputs are placed in a high-impedance

state, but the contents of the registers are preserved.

GRST

Y12

P11

Global reset. When the global reset is asserted, the GRST signal causes the PCI4451 to

place all output buffers in a high-impedance state and reset all internal registers. When

GRST is asserted, the device is completely in its default state. For systems that require

wake-up from D3, GRST will normally be asserted only during initial boot. PRST should be

asserted following initial boot so that PME context is retained when transitioning from D3 to

D0. For systems that do not require wake-up from D3, GRST should be tied to PRST.

PCI4451 Datasheet(PDF) 32 Page - Texas Instruments

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