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PCI4451 Datasheet(PDF) 73 Page - Texas Instruments

Part # PCI4451
Description  PC CARD AND OHCI CONTROLLER
PDF  216 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

PCI4451 Datasheet(HTML) 73 Page - Texas Instruments

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4–5
4.6
Class Code and Revision ID Registers
The class code and revision ID register recognizes the PCI4451 functions 0 and 1 as a bridge device (06h) and
CardBus bridge device (07h) with a 00h programming interface. Furthermore, the TI chip revision is indicated in the
least significant byte (00h).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Class code and revision ID
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Class code and revision ID
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Class code and revision ID
Type:
Read-only
Offset:
08h (Functions 0, 1)
Default:
0607 0000h
4.7
Cache Line Size Register
The cache line size register is programmed by host software to indicate the system cache line size.
Bit
7
6
5
4
3
2
1
0
Name
Cache line size
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Register:
Cache line size
Type:
Read/Write
Offset:
0Ch (Functions 0, 1)
Default:
00h
4.8
Latency Timer Register
The latency timer register specifies the latency timer for the PCI4451, in units of PCI clock cycles. When the PCI4451
is a PCI bus initiator and asserts FRAME, the latency timer begins counting from zero. If the latency timer expires
before the PCI4451 transaction has terminated, then the PCI4451 terminates the transaction when its GNT is
deasserted.
Bit
7
6
5
4
3
2
1
0
Name
Latency timer
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Register:
Latency timer
Type:
Read/Write
Offset:
0Dh
Default:
00h



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