PCI4451 datasheet(95/216 Pages) TI

95 / 216 page

4–27

Table 4–15. Multifunction Routing Status Register Description (continued)

BIT

SIGNAL

TYPE

FUNCTION

RSVD

Reserved. This bit returns 0 when read. Writes have no effect.

10–8

MFUNC2_SEL

R/W

MFUNC2 select. These bits control the mapping of MFUNC2 as follows:

000 = GPI2

100 = D3_STAT

001 = GPO2

101 = RSVD

010 = INTC

110 = RSVD

011 = PCGNT

111 = C_ZVCLK

RSVD

Reserved. This bit returns 0 when read. Writes have no effect.

6–4

MFUNC1_SEL

R/W

MFUNC1 select. These bits control the mapping of MFUNC1 as follows:

000 = GPI1

100 = D3_STAT

001 = GPO1

101 = LOCK

010 = INTB

110 = CAUDPWM

011 = TEST_MUX

111 = ZV_STAT

RSVD

Reserved. This bit returns 0 when read. Writes have no effect.

2–0

MFUNC0_SEL

R/W

MFUNC0 select. These bits control the mapping of MFUNC0 as follows:

000 = GPI0

100 = RSVD

001 = GPO0

101 = GPE

010 = INTA

110 = RSVD

011 = PCREQ

111 = ZV_STAT

PCI4451 Datasheet(PDF) 95 Page - Texas Instruments

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