PCI4451 datasheet(96/216 Pages) TI

96 / 216 page

4–28

4.37 Retry Status Register

The contents of the retry status register enable the retry time-out counters and display the retry expiration status. The

flags are set when the PCI4451 retries a PCI or CardBus master request, and the master does not return within 215

PCI clock cycles. The flags are cleared by writing a 1 to the bit. These bits are expected to be incorporated into the

PCI command register, status register, and bridge control register (offset 3Eh, see Section 4.24) by the PCI SIG.

Access this register only through function 0. See Table 4–16 for a complete description of the register contents.

Bit

Name

Retry status

Type

R/W

Default

Retry status

Type:

Read-only, Read/Write, Read/Clear

Offset:

90h (Functions 0, 1)

Default:

C0h

Table 4–16. Retry Status Register Description

BIT

SIGNAL

TYPE

FUNCTION

PCIRETRY

R/W

PCI retry time-out counter enable. This bit is encoded as:

0 = PCI retry counter disabled

1 = PCI retry counter enabled (default)

6§

CBRETRY

R/W

CardBus retry time-out counter enable. This bit is encoded as:

0 = CardBus retry counter disabled

1 = CardBus retry counter enabled (default)

TEXP_CBB

CardBus target B retry expired. Write a 1 to clear this bit.

0 = Inactive (default)

1 = Retry has expired.

RSVD

Reserved. This bit returns 0 when read.

3§

TEXP_CBA

CardBus target A retry expired. Write a 1 to clear this bit.

0 = Inactive (default)

1 = Retry has expired.

RSVD

Reserved. This bit returns 0 when read.

TEXP_PCI

PCI target retry expired. Write a 1 to clear this bit.

0 = Inactive (default)

1 = Retry has expired.

RSVD

Reserved. This bit returns 0 when read.

§ These bits are global in nature and should be accessed only through function 0.

PCI4451 Datasheet(PDF) 96 Page - Texas Instruments

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