PCI4451 datasheet(98/216 Pages) TI

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4–30

4.39 Device Control Register

The device control register is provided for PCI1130 compatibility. It contains bits which are shared between functions

0 and 1. The interrupt mode select is programmed through this register. The socket capable force bits are also

programmed through this register. See Table 4–18 for a complete description of the register contents.

Bit

Name

Device control

Type

R/W

Default

Device control

Type:

Read-only, Read/Write

Offset:

92h (Functions 0, 1)

Default:

66h

Table 4–18. Device Control Register Description

BIT

SIGNAL

TYPE

FUNCTION

SKTPWR_LOCK

R/W

Socket power lock bit. When this bit is set to 1, software will not be able to power down the PC Card

socket while in D3. This may be necessary to support Wake on LAN or RING if the operating system

is programmed to power down a socket when the CardBus controller is placed in the D3 state.

6§

3VCAPABLE

R/W

3-V socket capable force bit.

0 = Not 3-V capable

1 = 3-V capable (default)

IO16R2

R/W

Diagnostic bit. This bit defaults to 1.

RSVD

Reserved. This bit returns 0 when read. A write has no effect.

3§

TEST

R/W

TI test bit. Write only 0 to this bit. This bit can be set to shorten the interrogation counter.

2–1§

INTMODE

R/W

Interrupt mode. These bits select the interrupt signaling mode. The interrupt mode bits are encoded:

00 = Parallel PCI interrupts only

01 = Reserved

10 = IRQ serialized interrupts and parallel PCI interrupts INTA and INTB

11 = IRQ & PCI serialized interrupts (default)

0§

RSVD

R/W

Reserved. NAND tree enable bit. There is a NAND tree diagnostic structure in the PCI4451, and it tests

only the pins that are inputs or I/Os. Any output-only terminal on the PCI4451 is excluded from the

NAND tree test.

§ These bits are global in nature and should be accessed only through function 0.

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