PCI4451 datasheet(85/216 Pages) TI

85 / 216 page

4–17

4.28 System Control Register

System level initializations are performed through programming this doubleword register. Some of the bits are global

in nature and should be accessed only through function 0. See Table 4–7 for a complete description of the register

contents.

Bit

Name

System control

Type

R/W

Default

Bit

Name

System control

Type

R/W

Default

System control

Type:

Read-only, Read/Write

Offset:

80h (Functions 0, 1)

Default:

0000 0020h

Table 4–7. System Control Register Description

BIT

SIGNAL

TYPE

FUNCTION

31–30§

SER_STEP

R/W

Serialized PCI interrupt routing step. These bits are used to configure the serialized PCI interrupt stream

signaling and accomplish an even distribution of interrupts signaled on the four PCI interrupt slots. These

bits are global to both PCI4451 functions.

00 = INTA/INTB/INTC signal in INTA/INTB/INTC slots (default)

01 = INTA/INTB/INTC signal in INTB/INTC/INTD slots

10 = INTA/INTB/INTC signal in INTC/INTD/INTA slots

11 = INTA/INTB/INTC signal in INTD/INTA/INTB slots

29§

INTRTIE

R/W

Tie internal PCI interrupts. When this bit is set, the INTA and INTB signals are tied together internally and

are signaled as INTA. INTA may then be shifted by using the SER_STEP bits. This bit is global to both

PCI4451 functions. This bit has no effect on INTC.

0 = INTA and INTB are not tied together internally (default).

1 = INTA and INTB are tied together internally.

TIEALL

R/W

This bit ties INTA, INTB, and INTC internally (to INTA) and reports this through the interrupt pin register

(offset 3Dh, see Section 4.23).

27§

P2CCLK

R/W

P2C power switch CLOCK. This bit determines whether the CLOCK terminal (GFN terminal U12, GJG

terminal T11) is an input that requires an external clock source or if this terminal is an output that uses the

internal oscillator. Bit 27 can be set to enable the PCI4451 to generate and drive CLOCK from the PCI

clock.

0 = CLOCK privided externally, input to PCI4451 (default)

1 = CLOCK generated by PCI clock and driven by PCI4451

A 43-k

W pulldown resistor should be tied to this terminal.

26§

SMIROUTE

R/W

SMI interrupt routing. This bit is shared between functions 0 and 1, and selects whether IRQ2 or CSC is

signaled when a write occurs to power a PC Card socket.

0 = PC Card power change interrupts routed to IRQ2 (default).

1 = A CSC interrupt is generated on PC Card power changes.

SMISTATUS

R/W

SMI interrupt status. This socket-dependent bit is set when a write occurs to set the socket power, and

the SMIENB bit is set. Writing a 1 to this bit clears the status.

0 = SMI interrupt is signaled.

1 = SMI interrupt is not signaled.

24§

SMIENB

R/W

SMI interrupt mode enable. When this bit is set, the SMI interrupt signaling generates an interrupt when

a write to the socket power control occurs. This bit is shared and defaults to 0 (disabled).

0 = SMI interrupt mode is disabled (default).

1 = SMI interrupt mode is enabled.

§ These bits are global in nature and should be accessed only through function 0.

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