PCI4451 datasheet(49/216 Pages) TI

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3–5

SCL

SDA

VCC

SCL

SDA

PCI4451

Serial

EEPROM

Figure 3–3. Serial EEPROM Application

As stated above, when the PCI4451 is reset by G_RST, the subsystem data is read automatically from the EEPROM.

The PCI4451 masters the serial EEPROM bus and reads four bytes as described in Figure 3–4.

Slave Address

b6 b5 b4 b3 b2 b1 b0

b7 b6 b5 b4 b3 b2 b1 b0

b6 b5 b4 b3 b2 b1 b0

Word Address

Slave Address

R/W

Restart

R/W

Data Byte 0

Data Byte 1

Data Byte 2

Data Byte 3

S/P – Start/Stop Condition

A – Slave Acknowledgment

M – Master Acknowledgment

Start

Stop

Figure 3–4. EEPROM Interface Subsystem Data Collection

The EEPROM is addressed at word address A0h (1010 0000b), as indicated in Figure 3–4, and the address

auto-increments after each byte transfers according to the protocol. Thus, to provide the subsystem register with data

AABBCCDDh the EEPROM should be programmed with address 0 = AAh, 1 = BBh, 2 = CCh, and 3 = DDh.

The serial EEPROM is addressed at slave address 1010 000b by the PCI4451. All hardware address bits for the

EEPROM should be tied to the appropriate level to achieve this address. The serial EEPROM chip in the sample

application circuit, Figure 3–3, assumes the 1010b high address nibble. The lower three address bits are terminal

inputs to the chip, and the sample application shows these terminal inputs tied to GND.

The serial EEPROM interface signals require pullup resistors. The serial EEPROM protocol allows bidirectional

transfers. Both the SCL and SDA signals are placed in a high-impedance state and pulled high when the bus is not

active. When the SDA line transitions to a logic low, this signals a start condition (S). A low-to-high transition of SDA

while SCL is high is defined as the stop condition (P). One bit is transferred during each clock pulse. The data on the

SDA line must remain stable during the high period of the clock pulse, as changes in the data line at this time will be

interpreted as a control signal. Data is valid and stable during the clock high period. Figure 3–5 illustrates this protocol.

PCI4451 Datasheet(PDF) 49 Page - Texas Instruments

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