M3885 datasheet(37/103 Pages) RENESAS

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3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

[I2C Data Shift Register (S0)] 001216

The I2C data shift register (S0) is an 8-bit shift register to store re-

ceive data and write transmit data.

When transmit data is written into this register, it is transferred to

the outside from bit 7 in synchronization with the SCL clock, and

each time one-bit data is output, the data of this register are

shifted by one bit to the left. When data is received, it is input to

this register from bit 0 in synchronization with the SCL clock, and

each time one-bit data is input, the data of this register are shifted

by one bit to the left. The minimum 2 cycles of

φ are required from

the rising of the SCL clock until input to this register.

The I2C data shift register is in a write enable status only when the

I2C-BUS interface enable bit (ES0 bit : bit 3 S1D) of the I2C con-

trol register is “1”. The bit counter is reset by a write instruction to

the I2C data shift register. When both the ES0 bit and the MST bit

of the I2C status register (S1) are “1”, the SCL is output by a write

instruction to the I2C data shift register. Reading data from the I2C

data shift register is always enabled regardless of the ES0 bit

value.

[I2C Address Register (S0D)] 001316

The I2C address register (S0D) consists of a 7-bit slave address and

_______

a read/write bit. In the addressing mode, the slave address written in

this register is compared with the address data to be received imme-

diately after the START condition is detected.

_________

•Bit 0: Read/write bit (RWB)

This is not used in the 7-bit addressing mode. In the 10-bit ad-

dressing mode, the first address data to be received is compared

with the contents (SAD6 to SAD0 + RWB) of the I2C address reg-

ister.

The RWB bit is cleared to “0” automatically when the stop condi-

tion is detected.

•Bits 1 to 7: Slave address (SAD0–SAD6)

These bits store slave addresses. Regardless of the 7-bit address-

ing mode and the 10-bit addressing mode, the address data

transmitted from the master is compared these bits.

Fig. 32 Structure of I2C address register

SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RWB

Slave address

I2C address register

(S0D: address 001316)

Read/write bit

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