M3885 datasheet(28/103 Pages) RENESAS

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3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

WATCHDOG TIMER

The watchdog timer gives a mean of returning to the reset status

when a program cannot run on a normal loop (for example, be-

cause of a software run-away). The watchdog timer consists of an

8-bit watchdog timer L and an 8-bit watchdog timer H.

Basic Operation of Watchdog Timer

When any data is not written into the watchdog timer control reg-

ister (WDTCON) after resetting, the watchdog timer is in the stop

state. The watchdog timer starts to count down by writing an op-

tional value into the watchdog timer control register (WDTCON) and

an internal reset occurs at an underflow of the watchdog timer H.

Accordingly, programming is usually performed so that writing to

the watchdog timer control register (WDTCON) may be started be-

fore an underflow. When the watchdog timer control register

(WDTCON) is read, the values of the high-order 6 bits of the

watchdog timer H, STP instruction disable bit, and watchdog timer

H count source selection bit are read.

Initial Value of Watchdog Timer

At reset or writing to the watchdog timer control register

(WDTCON), each watchdog timer H and L is set to “FF16”.

Fig. 22 Structure of Watchdog timer control register

qWatchdog timer H count source selection bit operation

Bit 7 of WDTCON permits selecting a watchdog timer H count

source. When this bit is set to “0”, the count source becomes the

underflow signal of watchdog timer L. The detection time is set to

131.072 ms at f(XIN)=8 MHz and 32.768 s at f(XCIN)=32 kHz .

When this bit is set to “1”, the count source becomes the signal

divided by 16 for f(XIN) (or f(XCIN) in low speed mode). The detec-

tion time in this case is set to 512

µs at f(XIN)=8 MHz and 128 ms

at f(XCIN)=32 kHz . This bit is cleared to “0” after resetting.

qSTP instruction disable bit

Bit 6 of WDTCON permits disabling the STP instruction when the

watchdog timer is in operation.

When this bit is “0”, the STP instruction is enabled.

When this bit is “1”, the STP instruction is disabled.

When this bit is “1”, the STP instruction execution cause an inter-

nal reset. When this bit is set to “1”, it cannot be rewritten to “0” by

program. This bit is cleared to “0” after resetting.

Fig. 21 Block diagram of Watchdog timer

XIN

Data bus

XCIN

“10”

“00”

“01”

Main clock division

ratio selection bits

(Note)

“0”

“1”

1/16

Watchdog timer H count

source selection bit

Reset

circuit

STP instruction disable bit

Watchdog timer H (8)

“FF16” is set when

watchdog timer

control register is

written to.

Internal reset

RESET

Watchdog timer L (8)

Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.

STP instruction

“FF16” is set when

watchdog timer

control register is

written to.

STP instruction disable bit

0: STP instruction enabled

1: STP instruction disabled

Watchdog timer H count source selection bit

0: Watchdog timer L underflow

1: f(XIN)/16 or f(XCIN)/16

Watchdog timer H (for read-out of high-order 6 bit)

Watchdog timer control register

(WDTCON : address 001E16)

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