M3885 datasheet(23/103 Pages) RENESAS

23 / 103 page

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

Fig. 15 Interrupt control

Fig. 16 Structure of interrupt-related registers (1)

Interrupt disable flag (I)

Interrupt request

Interrupt request bit

Interrupt enable bit

BRK instruction

Reset

0 : No interrupt request issued

1 : Interrupt request issued

Interrupt request register 2

CNTR0/INT0 interrupt request bit

CNTR1/INT1 interrupt request bit

I2C interrupt request bit

INT2 interrupt request bit

INT3 interrupt request bit

INT4 interrupt request bit

AD converter/key-on wake-up interrupt

request bit

Not used (returns “0” when read)

(IREQ2 : address 003D16)

Interrupt control register 2

CNTR0/INT0 interrupt enable bit

CNTR1/INT1 interrupt enable bit

I2C interrupt enable bit

INT2 interrupt enable bit

INT3 interrupt enable bit

INT4 interrupt enable bit

AD converter/key-on wake-up interrupt

enable bit

Not used (returns “0” when read)

(Do not write “1” to this bit)

0 : Interrupts disabled

1 : Interrupts enabled

(ICON2 : address 003F16)

Interrupt edge selection register

INT0 active edge selection bit

INT1 active edge selection bit

Not used (returns “0” when read)

INT2 active edge selection bit

INT3 active edge selection bit

INT4 active edge selection bit

INT5 active edge selection bit

Not used (returns “0” when read)

(INTEDGE : address 003A16)

Interrupt request register 1

INT0/input buffer full interrupt request

bit

INT1/output buffer empty interrupt

request bit

Serial I/O receive interrupt/LRESET

request bit

Serial I/O transmit/SCL, SDA interrupt

request bit

Timer X interrupt request bit

Timer Y interrupt request bit

Timer 1 interrupt request bit

Timer 2/INT5 interrupt request bit

Interrupt control register 1

INT0/input buffer full interrupt enable bit

INT1/output buffer empty interrupt enable

bit

Serial I/O receive interrupt/LRESET

enable bit

Serial I/O transmit/SCL, SDA interrupt

enable bit

Timer X interrupt enable bit

Timer Y interrupt enable bit

Timer 1 interrupt enable bit

Timer 2/INT5 interrupt enable bit

(IREQ1 : address 003C16)

(ICON1 : address 003E16)

0 : Falling edge active

1 : Rising edge active

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