M3885 datasheet(67/103 Pages) RENESAS

67 / 103 page

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

COMPARATOR CIRCUIT

Comparator Configuration

The comparator circuit consists of the ladder resistors, the analog

comparators, a comparator control circuit, the comparator refer-

ence input selection bit (bit 7 of PCTL2), a comparator data

(P20/CMPREF) and analog input pins (P30–P37). The analog input

pin (P30–P37) also functions as an ordinary digital port.

Comparator Operation

To activate the comparator circuit, first set port P3 to input mode

by setting the corresponding direction register (P3D) to “0” to use

port P3 as an analog voltage input pin. The internal fixed analog

voltage (VCC ✕ 29/32) can be generated by setting “1” to the com-

parator reference input selection bit (bit 7 of PCTL2). The internal

fixed analog voltage becomes about 2.99 V at VCC = 3.3 V. When

setting “0” to the comparator reference input selection bit, the P20/

CMPREF pin becomes the comparator reference power source in-

put pin and it is possible to input the comparator reference power

source optionally from the external. The voltage comparison is im-

mediately performed by the writing operation to the comparator

data register (CMPD). After 14 cycles of the internal system clock

φ (the time required for the comparison), the comparison result is

stored in the comparator data register (CMPD).

If the analog input voltage is greater than the internal reference

voltage, each bit of this register is “1”; if it is less than the internal

reference voltage, each bit of this register is “0”. To perform an-

other comparison, the voltage comparison must be performed

again by writing to the comparator data register (CMPD).

Read the result when 14 cycles of

φ or more have passed after the

comparator operation starts. The ladder resistor is turned on dur-

ing 14 cycles of

φ , which is required for the comparison, and the

reference voltage is generated. An unnecessary current is not

consumed because the ladder resistor is turned off while the com-

parator operation is not performed. Since the comparator consists

of capacitor coupling, the electric charge may lost if the clock fre-

quency is low.

Keep the clock frequency more than 1 MHz during the comparator

operation. Do not execute the STP, WIT, or port P3 I/O instruction.

Fig. 64 Comparator circuit

VSS

VCC

P3 (8)

P37

P36

P30

Comparator reference input selection bit

(bit 7 of PCTL2)

Comparator data register

Compar-

ator

Ladder resistor

connecting signal

Comparator

control circuit

Comparator connecting

signal

Compar-

ator

Compar-

ator

P20/CMPREF

VCC✕29/32

“1”

“0”

Data bus

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