| Electronic Components Datasheet Search |
|
M3885 Datasheet(PDF) 82 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
M3885 Datasheet(HTML) 82 Page - Renesas Technology Corp |
|
82 / 103 page ![]() 3885 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 81 Fig. 77 Flash memory control registers Fig. 78 CPU rewrite mode set/reset flowchart Flash memory control register (address 0FFE16) FMCR RY/BY status flag (FMCR0) 0: Busy (being programmed or erased) 1: Ready CPU reprogram mode select bit (FMCR1) (Note 2) 0: Normal mode (Software commands invalid) 1: CPU rewrite mode (Software commands acceptable) CPU reprogram mode entry flag (FMCR2) 0: Normal mode 1: CPU rewrite mode Flash memory reset bit (FMCR3) (Note 3) 0: Normal operation 1: Reset User ROM area / Boot ROM area select bit (FMCR4) (Note 4) 0: User ROM area accessed 1: Boot ROM area accessed Reserved bits (Indefinite at read/ “0” at write) b0 b7 Notes1: The contents of flash memory control register are “XXX00001” just after reset release. 2: For this bit to be set to “1”, the user needs to write “0” and then “1” to it in succession. If it is not this procedure, this bit will not be set to ”1”. Additionally, it is required to ensure that no interrupt will be generated during that interval. Use the control program in the area except the built-in flash memory for write to this bit. 3: This bit is valid when the CPU rewrite mode select bit is “1”. Set this bit 3 to “0” subsequently after setting bit 3 to “1”. 4: Use the control program in the area except the built-in flash memory for write to this bit. End Start Execute read array command or reset flash memory by setting flash memory reset bit (by writing “1” and then “0” in succession) (Note 2) Single-chip mode, or boot mode Set CPU mode register (Note 1) Using software command execute erase, program, or other operation Jump to transferred control program in RAM (Subsequent operations are executed by control program in this RAM) Transfer CPU reprogram mode control program to internal RAM Notes 1: Set bit 6,7 (Main clock division ratio selection bits ) at CPU mode register (003B16). 2: Before exiting the CPU reprogram mode after completing erase or program operation, always be sure to execute a read array command or reset the flash memory. Write “0” to CPU reprogram mode select bit Set CPU reprogram mode select bit to “1” (by writing “0” and then “1” in succession)(Note 3) Check the CPU reprogram mode entry flag *1 *1 Program in ROM Program in RAM |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |