M3885 datasheet(74/103 Pages) RENESAS

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3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

Bus Operation Modes

Read

_____

The Read mode is entered by pulling the OE pin low when the CE

_____

pin is low and the WE and RP pins are high. There are two read

modes: array, and status register, which are selected by software

command input. In read mode, the data corresponding to each soft-

ware command entered is output from the data I/O pins D0–D7. The

read array mode is automatically selected when the device is pow-

ered on or after it exits deep power down mode.

Output Disable

_____

The output disable mode is entered by pulling the CE pin low and the

_____

WE, OE, and RP pins high. Also, the data I/O pins are placed in the

high-impedance state.

Standby

_____

The standby mode is entered by driving the CE pin high when the RP

pin is high. Also, the data I/O pins are placed in the high-impedance

_____

state. However, if the CE pin is set high during erase or program

operation, the internal control circuit does not halt immediately and

normal power consumption is required until the operation under way

is completed.

Write

_____

The write mode is entered by pulling the WE pin low when the CE pin

_____

is low and the OE and RP pins are high. In this mode, the device

accepts the software commands or write data entered from the data

I/O pins. A program, erase, or some other operation is initiated de-

pending on the content of the software command entered here. The

input data such as address and software command is latched at the

_____

rising edge of WE or CE whichever occurs earlier.

Deep Power Down

_____

The deep power down is entered by pulling the RP pin low. Also, the

data I/O pins are placed in the high-impedance state. When the de-

vice is freed from deep power down mode, the read array mode is

selected and the content of the status register is set to “8016.” If the

_____

RP pin is pulled low during erase or program operation, the opera-

tion under way is canceled and the data in the relevant block be-

comes invalid.

User ROM and Boot ROM Areas

In parallel I/O mode, the user ROM and boot ROM areas shown in Fig-

ure 72 can be rewritten. The BSEL pin is used to choose between these

two areas. The user ROM area is selected by pulling the BSEL input

low; the boot ROM area is selected by driving the BSEL input high. Both

areas of flash memory can be operated on in the same way.

Program and block erase operations can be performed in the user ROM

area. The user ROM area and its blocks are shown in Figure 72.

The user ROM area is 60 Kbytes in size. In parallel I/O mode, it is

located at addresses 100016 through FFFF16. The boot ROM area is

4 Kbytes in size. In parallel I/O mode, it is located at addresses

F00016 through FFFF16. Make sure program and block erase opera-

tions are always performed within this address range. (Access to any

location outside this address range is prohibited.)

In the Boot ROM area, an erase block operation is applied to only

one 4 Kbyte block.

Functional Outline (Parallel I/O Mode)

In parallel I/O mode, bus operation modes—Read, Output Disable,

Standby, Write, and Deep Power Down—are selected by the status

_____

of the CE, OE, WE, and RP input pins.

The contents of erase, program, and other operations are selected

by writing a software command. The data, status register, etc. in

memory can only be read out by a read after software command

input.

Program and erase operations are controlled using software com-

mands.

The following explains about bus operation modes, software com-

mands, and status register.

D0 to D7

Data output

Status register data output

Hi-z

Command/data input

Command input

Hi-z

_____

VIH

VIL

______

VIH

VIL

_____

VIL

VIH

_____

VIL

VIH

VIL

Pin name

Mode

Array

Status register

Output disabled

Stand by

Program

Write

Erase

Other

Deep power down

Read

Note : X can be VIL or VIH.

Table 19 Relationship between control signals and bus operation modes

Parallel I/O Mode

The parallel I/O mode is entered by making connections shown in

Figures 73 and then turning the Vcc power supply on.

Address

The user ROM is divided into two blocks as shown in Figure 72. The

block address referred to in this data sheet is the maximum address

value of each block.

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