M3885 datasheet(29/103 Pages) RENESAS

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3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

PULSE WIDTH MODULATION (PWM)

OUTPUT CIRCUIT

The 3885 group has two PWM output circuits, PWM0 and PWM1,

with 14-bit resolution respectively. These can operate indepen-

dently. When the oscillation frequency XIN is 8 MHz, the minimum

Fig. 23 PWM block diagram (PWM0)

resolution bit width is 250 ns and the cycle period is 4096

µs. The

PWM timing generator supplies a PWM control signal based on a

signal that is the frequency of the XIN clock.

The following explanation assumes f(XIN) = 8 MHz.

1/2

PWM0 enable bit

P30 latch

P30/PWM00

PWM0L register (Address 003116)

PWM0H register (Address 003016)

bit 7

bit 0

bit 5

MSB

LSB

PWM0

bit 7

bit 0

PWM0

timing

generator

(64

µs period)

(4096

µs period)

PWM0 latch (14 bits)

Set to “1”

at write

Data Bus

f(XIN)

(8MHz)

14-bit PWM0 circuit

P56 direction register

PWM0 enable bit

P56 latch

P56/DA1/PWM01

PWM0 output selection bit

P30 direction register

(4MHz)

PWM0 enable bit

PWM0 output selection bit

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