M3885 datasheet(45/103 Pages) RENESAS

45 / 103 page

3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

Example of Master Transmission

An example of master transmission in the standard clock mode, at

the SCL frequency of 100 kHz and in the ACK return mode is

shown below.

(1) Set a slave address in the high-order 7 bits of the I2C address

(2) Set the ACK return mode and SCL = 100 kHz by setting “8516”

in the I2C clock control register (S2).

(3) Set “0016” in the I2C status register (S1) so that transmission/

reception mode can become initializing condition.

(4) Set a communication enable status by setting “0816” in the I2C

control register (S1D).

(5) Confirm the bus free condition by the BB flag of the I2C status

(6) Set the address data of the destination of transmission in the

high-order 7 bits of the I2C data shift register (S0) and set “0”

in the least significant bit.

(7) Set “F016” in the I2C status register (S1) to generate a START

condition. At this time, an SCL for 1 byte and an ACK clock au-

tomatically occur.

(8) Set transmit data in the I2C data shift register (S0). At this time,

an SCL and an ACK clock automatically occur.

(9) When transmitting control data of more than 1 byte, repeat step

(8).

(10) Set “D016” in the I2C status register (S1) to generate a STOP

condition if ACK is not returned from slave reception side or

transmission ends.

Example of Slave Reception

An example of slave reception in the high-speed clock mode, at

the SCL frequency of 400 kHz, in the ACK non-return mode and

using the addressing format is shown below.

(1) Set a slave address in the high-order 7 bits of the I2C address

(2) Set the no ACK clock mode and SCL = 400 kHz by setting

“2516” in the I2C clock control register (S2).

(3) Set “0016” in the I2C status register (S1) so that transmission/

reception mode can become initializing condition.

(4) Set a communication enable status by setting “0816” in the I2C

control register (S1D).

(5) When a START condition is received, an address comparison

is performed.

(6)•When all transmitted addresses are “0” (general call):

AD0 of the I2C status register (S1) is set to “1” and an interrupt

request signal occurs.

• When the transmitted address matches with the address set

in (1):

ASS of the I2C status register (S1) is set to “1” and an interrupt

request signal occurs.

• In the cases other than the above AD0 and AAS of the I2C

status register (S1) are set to “0” and no interrupt request sig-

nal occurs.

(7) Set dummy data in the I2C data shift register (S0).

(8) When receiving control data of more than 1 byte, repeat step (7).

(9) When a STOP condition is detected, the communication ends.

sPrecautions when using multi-master I2C-

BUS interface

(1) Read-modify-write instruction

The precautions when the read-modify-write instruction such as

SEB, CLB etc. is executed for each register of the multi-master

I2C-BUS interface are described below.

• I2C data shift register (S0: address 001216)

When executing the read-modify-write instruction for this regis-

ter during transfer, data may become a value not intended.

• I2C address register (S0D: address 001316)

When the read-modify-write instruction is executed for this regis-

ter at detecting the STOP condition, data may become a value

not intended. It is because H/W changes the read/write bit

(RWB) at the above timing.

• I2C status register (S1: address 001416)

Do not execute the read-modify-write instruction for this register

because all bits of this register are changed by H/W.

• I2C control register (S1D: address 001516)

When the read-modify-write instruction is executed for this regis-

ter at detecting the START condition or at completing the byte

transfer, data may become a value not intended. Because H/W

changes the bit counter (BC0-BC2) at the above timing.

• I2C clock control register (S2: address 001616)

The read-modify-write instruction can be executed for this register.

• I2C START/STOP condition control register (S2D: address

001716)

The read-modify-write instruction can be executed for this register.

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