M3885 datasheet(97/103 Pages) RENESAS

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3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

Table 37 Timing requirements

(VCC = 3.3 V ± 0.3V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Reset input “L” pulse width

Main clock input cycle time

Main clock input “H” pulse width

Main clock input “L” pulse width

Sub-clock input cycle time

Sub-clock input “H” pulse width

Sub-clock input “L” pulse width

CNTR0, CNTR1 input cycle time

CNTR0, CNTR1 input “H” pulse width

CNTR0, CNTR1 input “L” pulse width

tW(RESET)

tC(XIN)

tWH(XIN)

tWL(XIN)

tC(XCIN)

tWH(XCIN)

tWL(XCIN)

tC(CNTR)

tWH(CNTR)

tWL(CNTR)

tWH(INT)

tWL(INT)

Limits

tc(XIN)

µs

Parameter

Min.

125

200

Typ.

Max.

Symbol

Unit

Note : When bit 6 of SIOCON is “1” (clock synchronous).

Divide this value by four when bit 6 of SIOCON is “0” (UART).

tC(SCLK1)

tWH(SCLK1)

tWL(SCLK1)

tsu(RxD-SCLK1)

th(SCLK1-RxD)

Serial I/O clock input cycle time (Note)

Serial I/O clock input “H” pulse width (Note)

Serial I/O clock input “L” pulse width (Note)

Serial I/O input setup time

Serial I/O input hold time

INT0, INT1, INT20, INT30, INT40, INT21, INT31, INT41

input “H” pulse width

INT0, INT1, INT20, INT30, INT40, INT21, INT31, INT41

input “L” pulse width

800

370

220

100

Table 38 Switching characteristics

(VCC = 3.3 V ± 0.3V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Serial I/O clock output “H” pulse width

Serial I/O clock output “L” pulse width

Serial I/O output delay time (Note 1)

Serial I/O output valid time (Note 1)

Serial I/O clock output rising time

Serial I/O clock output falling time

CMOS output rising time (Note 2)

CMOS output falling time (Note 2)

tWH (SCLK)

tWL (SCLK)

td (SCLK-TXD)

tV (SCLK-TXD)

tr (SCLK)

tf (SCLK)

tr (CMOS)

tf (CMOS)

Limits

Parameter

Min.

tC(SCLK)/2–30

–30

Typ.

Max.

140

Symbol

Unit

Notes 1: When the P45/TXD P-channel output disable bit (bit 4 of UARTCON) is “0”.

2: The XOUT pin is excluded.

Test

conditions

Fig. 90

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