M3885 datasheet(71/103 Pages) RENESAS

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3885 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

Fig. 70 System clock generating circuit block diagram (Single-chip mode)

WIT instruction

STP instruction

Timing

φ (internal clock)

STP instruction

Main clock stop bit

1/2

1/4

XIN

XOUT

XCOUT

XCIN

Interrupt request

Reset

Interrupt disable flag l

1/2

Port XC

switch bit

“1”

“0”

Low-speed mode

High-speed or

middle-speed

mode

Middle-speed mode

High-speed or

low-speed mode

Main clock division ratio

selection bits (Note 1)

Notes 1: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.

When low-speed mode is selected, set port Xc switch bit (b4) to “1”.

2: f(XIN)/16 is supplied as the count source to the Prescaler 12 at reset. When exciting STP instruction, the count source

does not change either f(XIN))/16 or f(XCIN))/16 after releasing stop mode. Oscillation stabilizing time is not fixed “01FF16”

when the bit 6 of PCTL2 is “1”.

Main clock division ratio

selection bits (Note1)

FF16

0116

Prescaler 12

Timer 1

Reset or

STP instruction

(Note 2)

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