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DP83261 Datasheet(PDF) 28 Page - National Semiconductor (TI) |
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DP83261 Datasheet(HTML) 28 Page - National Semiconductor (TI) |
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28 / 132 page ![]() 60 Control Information (Continued) Option Register (Option) The Ring Engine supports several options These options are typically static during operation but may be altered during operation This register is initialized to Zero after a master reset ACCESS RULES Address Read Write 01h Always Always REGISTER BITS D7 D6 D5 D4 D3 D2 D1 D0 ITC EMIND IFCS IRPT IRR ITR ELA ESA Bit Symbol Description D0 ESA Enable Short Addressing Enables the setting of A Flag on matches of received Short Destination Addresses with MSA Enables the setting of M Flag and stripping on matches of received Short Source Addresses with MSA Permits transmission of frames with Short Addresses Frames with Short Addresses can be transmitted when Short Addressing is not enabled if the SA Transparency option is selected Void frames are sent with the Short Address if ESA is set to One If ESA is Zero and ELA is One Void frames are sent with the Long Address When both the ESA and ELA bits are Zero the ring is effectively interrupted at this station The token capture process and Error Recovery logic are suspended and no frames are repeated Immediate requests are serviced if the SA Transparency option is selected D1 ELA Enable Long Addressing Enables the setting of A Flag on matches of received Long Destination Addresses with MLA Enables the setting of M Flag and stripping on matches of received Long Source Address with MLA Permits transmission of frames with Long Addresses Frames with long addresses can be transmitted when long addressing is not enabled if the SA transparency option is selected Claim and Beacon frames are sent with the Long Address if ELA is One If ELA is Zero and ESA is One Claim and Beacon frames are sent with the Short Address When both ESA and ELA are Zero the ring is effectively interrupted at this station The token capture process and Error Recovery logic are suspended and no frames are repeated Immediate requests are serviced if the SA Transparency option is selected D2 ITR Inhibit Token Release When bit ITR is set to One the station will not issue a token after winning the Claim Process The station remains in the Claim state while the station’s Claim frames are returning to the station and it has won the Claim Process At this point the station is in control of the ring as long as no Higher Claim or Beacon frames are received While in control of the ring the station may transmit special Claim or Management frames for a variety of implementation specific purposes For example the station might send out a Claim frame with a unique identifier to make sure that another station with its address and TREQ is not also Claiming D3 IRR Inhibit Recovery Required When bit IRR is set to One the Ring Engine does not take the transitions into the Claim state (T4) This option inhibits all the recovery required transitions as defined in the FDDI MAC Standard This bit does not inhibit entry to the Claim state on a Claim Request generated at the MAC Request Interface via the Function Register This option can be used to guarantee that implementation specific Beacon frames will be transmitted from the Beacon state It is also useful in systems where Local Address Administration is used to prohibit stations with the Null Address (or any address) from Claiming The option could also be used to enable the use of the Ring Engine in full duplex applications (in conjunction with the Inhibit Repeat option) to disable the recovery timers 28 |
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