DP83261 datasheet(3/132 Pages) NSC

3 / 132 page

10 FDDI Chip Set Overview

National Semiconductor’s DP83200 FDDI chip set consists

of five components as shown in

Figure 1-1 For more infor-

mation on the other devices of the chip set consult the

appropriate datasheets and application notes

DP8325656-AP57 PLAYERa TM

Device Physical Layer Controller

The PLAYERa device implements the Physical Layer

(PHY) protocol as defined by the ANSI FDDI PHY X3T95

Standard along with all the necessary clock recovery and

clock regeneration functions

Features

Single chip FDDI Physical Layer (PHY) solution

Integrated Digital Clock Recovery Module provides en-

hanced tracking and greater lock acquisition range

Integrated Clock Generation Module provides all neces-

sary clock signals for an FDDI system from an external

125 MHz reference

Alternate PMD Interface (DP83256-AP57) supports

UTP twisted pair FDDI PMDs with no external clock re-

covery or clock generation functions required

No External Filter Components

Connection Management (CMT) Support (LEM TNE

React CF

React Auto Scrubbing)

Full on-chip configuration switch

Low Power CMOS-BIPOLAR design using a single 5V

supply

Full duplex operation with through parity

Separate management interface (Control Bus)

Selectable Parity on PHY-MAC Interface and Control Bus

Interface

Two levels of on-chip loopback

4B5B encoderdecoder

Framing logic

Elasticity Buffer Repeat Filter and Smoother

Line state detectorgenerator

Supports single attach stations dual attach stations and

concentrators with no external logic

DP8325656-AP for SASDAS single path stations

P83257 for SASDAS singledual path stations

addition

the

DP83257

contains

additional

PHY

Datarequest and PHY

Dataindicate port required

for concentrators and dual attach stations

DP83261 BMACTM Device

Media Access Controller

The BMAC device implements the Timed Token Media Ac-

cess Control protocol defined by the ANSI X3T95 FDDI

MAC Standard

Features

All of the standard defined ring service options

Full duplex operation with through parity

Supports all FDDI Ring Scheduling Classes (Synchro-

nous Asynchronous etc)

Supports Individual Group Short Long and External

Addressing

Generates Beacon Claim and Void frames internally

Extensive ring and station statistic gathering

Extensions for MAC level bridging

Separate management port that is used to configure and

control operation

Multi-frame streaming interface

DP83265A BSI-2 Device

System Interface

The BSI-2 device implements an interface between the

BMAC device and a host system

Features

Fully software and pin compatible with the original BSI

device

Over 2 kbytes of on-chip FIFO

Operates from 125 MHz to 33 MHz synchronously with

host system

Provides Address bit swapping capability

Reduces interface logic for SBus adapters

32-bit wide AddressData path with byte parity

Programmable transfer burst sizes of 4 or 8 32-bit words

Interfaces to DRAMs or directly to system bus

2 Output and 3 Input Channels

Supports HeaderInfo splitting

Bridging support

Programmable Big or Little Endian alignment

Full duplex data path

Receive frame filtering services

DP83261 Datasheet(PDF) 3 Page - National Semiconductor (TI)

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