iCE40 LP/HX Family

Data Sheet

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FPGA-DS-02029-3.5

33

4.24. External Switching Characteristics – HX Devices

Over recommended operating conditions.

Parameter

Description

Device

Min.

Max.

Units

Clock

Global Clocks

Frequency for Global Buffer Clock network

All iCE40 HX devices

—

275

MHz

Clock Pulse Width for Global Buffer

All iCE40 HX devices

0.88

—

ns

Global Buffer Clock Skew Within a Device

iCE40HX1K

—

727

ps

iCE40HX4K

—

300

ps

iCE40HX8K

—

300

ps

Pin-LUT-Pin Propagation Delay

Best case propagation delay through one LUT-4

All iCE40 HX devices

—

7.30

ns

General I/O Pin Parameters (Using Global Buffer Clock without PLL)

Data bus skew across a bank of IOs

iCE40HX1K

—

696

ps

iCE40HX4K

—

290

ps

iCE40HX8K

—

290

ps

Clock to Output - PIO Output Register

iCE40HX1K

—

5.00

ns

iCE40HX4K

—

5.41

ns

iCE40HX8K

—

5.41

ns

Clock to Data Setup - PIO Input Register

iCE40HX1K

—

ns

iCE40HX4K

—

ns

iCE40HX8K

—

ns

Clock to Data Hold - PIO Input Register

iCE40HX1K

1.92

—

ns

iCE40HX4K

2.38

—

ns

iCE40HX8K

2.38

—

ns

Clock to Output - PIO Output Register

iCE40HX1K

—

2.96

ns

iCE40HX4K

—

2.51

ns

iCE40HX8K

—

2.51

ns

Clock to Data Setup - PIO Input Register

iCE40HX1K

3.10

—

ns

iCE40HX4K

4.16

—

ns

iCE40HX8K

4.16

—

ns

Clock to Data Hold - PIO Input Register

iCE40HX1K

–0.60

—

ns

iCE40HX4K

–0.53

—

ns

iCE40HX8K

–0.53

—

ns

Notes:

1.

Exact performance may vary with device and design implementation. Commercial timing numbers are shown at 85 °C and 1.14

V. Other operating conditions, including industrial, can be extracted from the iCECube2 software.

2.

General I/O timing numbers based on LVCMOS 2.5, 0pf load.

3.

Supported on devices with a PLL.