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ICE40 Datasheet(PDF) 36 Page - Lattice Semiconductor

Part # ICE40
Description  iCE40 LP/HX Family
PDF  52 Pages
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Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

ICE40 Datasheet(HTML) 36 Page - Lattice Semiconductor

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iCE40 LP/HX Family
Data Sheet
© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
36
FPGA-DS-02029-3.5
4.27. sysCONFIG Port Timing Specifications
Table 4.29. sysCONFIG Port Timing Specifications1
Symbol
Parameter
Min
Typ
Max
Unit
All Configuration Modes
t
CRESET_B
Minimum CRESET_B Low
pulse width required to
restart configuration, from
falling edge to rising edge
—
200
—
—
ns
t
DONE_IO
Number of configuration
clock cycles after CDONE goes
High before the PIO pins are
activated
—
49
—
—
Clock
Cycles
Slave SPI
t
CR_SCK
Minimum time from a rising
edge on CRESET_B until the
first SPI write operation, first
SPI_SCK. During this time, the
iCE40 device is clearing its
internal configuration
memory.
iCE40LP384
600
—
—
us
iCE40LP640, iCE40LP/HX1K
800
—
—
us
iCE40LP/HX4K
1200
—
—
us
iCE40LP/HX8K
1200
—
—
us
t
CR_SCK
Minimum time from a rising
edge on CRESET_B until the
first SPI write operation, first
SPI_SCK. During this time, the
iCE40 LP/HX device is clearing
its internal configuration
memory.
Write
1
—
25
MHz
Read iCE40LP384
2
—
15
—
MHz
Read iCE40LP640, iCE40LP/HX1K
2
—
15
—
MHz
Read iCE40LP/HX4K
2
—
15
—
MHz
Read iCE40LP/HX8K
2
—
15
—
MHz
t
CCLKH
CCLK clock pulse width high
—
20
—
—
ns
t
CCLKL
CCLK clock pulse width low
—
20
—
—
ns
t
STSU
CCLK setup time
—
12
—
ns
t
STH
CCLK hold time
—
12
—
—
ns
t
STCO
CCLK falling edge to valid
output
—
13
—
—
ns
Master SPI
f
MCLK
MCLK clock frequency
Off
—
0
—
MHz
Low Frequency (Default)
—
7.5
—
MHz
Medium Frequency
3
—
24
—
MHz
High Frequency
3
—
40
—
MHz
t
MCLK
CRESET_B high to first MCLK
edge
iCE40LP384 - Low Frequency (Default)
600
—
—
us
iCE40LP384 - Medium Frequency
600
—
—
us
iCE40LP384 - High Frequency
600
—
—
us
iCE40LP640, iCE40LP/HX1K - Low
Frequency (Default)
800
—
—
us
iCE40LP640, iCE40LP/HX1K - Medium
Frequency
800
—
—
us
iCE40LP640, iCE40LP/HX1K - High
Frequency
800
—
—
us
iCE40LP/HX1K -Low Frequency (Default)
800
—
—
us
iCE40LP/HX1K - Medium Frequency
800
—
—
us
iCE40LP/HX1K - High Frequency
800
—
—
us
iCE40LP/HX4K - Low Frequency (Default)
1200
—
—
us



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