ICE40 datasheet(21/52 Pages) LATTICE

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iCE40 LP/HX Family

Data Sheet

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02029-3.5

4.6. DC Electrical Characteristics

Over recommended operating conditions.

Table 4.5. DC Electrical Characteristics

Symbol

Parameter

Condition

Min

Typ

Max

Unit

IIL, IIH1, 3, 4, 5, 6, 7

Input or I/O Leakage

0 V < VIN < VCCIO + 0.2 V

—

±10

µA

C16, 7

I/O Capacitance2

VCCIO = 3.3 V, 2.5 V, 1.8 V

VCC = Typ, VIO = 0 to VCCIO + 0.2 V

—

C26, 7

Global Input Buffer

Capacitance2

VCCIO = 3.3 V, 2.5 V, 1.8 V

VCC = Typ, VIO = 0 to VCCIO + 0.2 V

—

VHYST

Input Hysteresis

VCCIO = 1.8 V, 2.5 V, 3.3 V

—

200

—

IPU6, 7

Internal PIO Pull-up

VCCIO = 1.8 V, 0 ≤ VIN ≤ 0.65 * VCCIO

−3

—

−31

µA

VCCIO = 2.5 V, 0 ≤ VIN ≤ 0.65 * VCCIO

−8

—

−72

µA

VCCIO = 3.3 V, 0 ≤ VIN ≤ 0.65 * VCCIO

−11

—

−128

µA

Notes:

Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is

not measured with the output driver active. Internal pull-up resistors are disabled.

TJ 25

oC, f = 1.0 MHz.

Refer to VIL and VIH in the sysI/O Single-Ended DC Electrical Characteristics table.

Only applies to I/Os in the SPI bank following configuration.

Some products are clamped to a diode when VIN is larger than VCCIO.

High current I/Os has three sysI/O buffers connected together.

The iCE40LP640 and iCE40LP1K SWG16 package has CDONE and a sysI/O buffer are connected together.

4.7. Static Supply Current – LP Devices

Table 4.6. Supply Current– LP Devices1, 2, 3, 4

Symbol

Parameter

Device

Typ VCC4

Unit

ICC

Core Power Supply

iCE40LP384

µA

iCE40LP640

100

µA

iCE40LP1K

100

µA

iCE40LP4K

250

µA

iCE40LP8K

250

µA

ICCPLL5, 6

PLL Power Supply

All devices

0.5

µA

IPP_2V5

NVCM Power Supply

All devices

1.0

µA

ICCIO, ICC_SPI

Bank Power Supply4

VCCIO = 2.5 V

All devices

3.5

µA

Notes:

Assumes blank pattern with the following characteristics: all outputs are tri-stated, all inputs are configured as LVCMOS and

held at VCCIO or GND, on-chip PLL is off. For more detail with your specific design, use the Power Calculator tool. Power specified

with master SPI configuration mode. Other modes may be up to 25% higher.

Frequency = 0 MHz.

TJ = 25 °C, power supplies at nominal voltage.

Does not include pull-up.

No PLL available on the iCE40LP384 and iCE40LP640 device.

VCCPLL is tied to VCC internally in packages without PLL pins.

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