iCE40 LP/HX Family

Data Sheet

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FPGA-DS-02029-3.5

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3.1.7. sysI/O Buffer

Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the

periphery of the device in groups referred to as banks. The sysI/O buffers allow users to implement a wide variety of

standards that are found in today’s systems including LVCMOS and LVDS25.

High Current LED Drivers combine three sysI/O buffers together. This allows for programmable drive strength. This also

allows for high current drivers that are ideal to drive three white LEDs, or one RGB LED. Each bank is capable of

supporting multiple I/O standards including single-ended LVCMOS buffers and differential LVDS25E output buffers.

Bank 3 additionally supports differential LVDS25 input buffers. Each sysI/O bank has its own dedicated power supply.

Typical I/O Behavior During Power-up

defined in Table 4.4. After the POR signal is deactivated, the FPGA core logic becomes active. It is your responsibility to

banks that are critical to the application. The default configuration of the I/O pins in a device prior to configuration is

banks containing configuration I/Os) have reached levels, at which time the I/Os will take on the software user-

configured settings only after a proper download/configuration. Unused I/Os are automatically blocked and the pull-up

termination is disabled.

Supported Standards

The iCE40 LP/HX sysI/O buffer supports both single-ended input/output standards, and used as differential

comparators. The buffer supports the LVCMOS 1.8 V, 2.5 V, and 3.3 V standards. The buffer has individually

configurable options for bus maintenance (weak pull-up or none).

iCE40 LP/HX devices.

Table 3.7. Supported Input Standards

I/O Standard

3.3 V

2.5 V

1.8 V

Single-Ended Interfaces

LVCMOS33

Yes

—

—

LVCMOS25

—

Yes

—

LVCMOS18

—

—

Yes

Differential Interfaces

LVDS25*

—

Yes

—

SubLVDS*

—

—

Yes

*Note: Bank 3 only.

Table 3.8. Supported Output Standards

I/O Standard

Single-Ended Interfaces

LVCMOS33

3.3 V

LVCMOS25

2.5 V

LVCMOS18

1.8 V

Differential Interfaces

LVDS25*

—

SubLVDS*

—

*Note: These interfaces can be emulated with external resistors in all devices.