iCE40 LP/HX Family

Data Sheet

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20

FPGA-DS-02029-3.5

4.3. Power Supply Ramp Rates

Table 4.3. Power Supply Ramp Rates*

Symbol

Parameter

Min

Max

Unit

t

RAMP

Power supply ramp rates for all

power supplies

All configuration modes. No power

supply sequencing.

0.40

10

V/ms

Configuring from Slave SPI. No power

supply sequencing,

0.01

10

V/ms

0.01

10

V/ms

0.01

10

V/ms

Notes:



Assumes monotonic ramp rates.



4.4. Power-On-Reset Voltage Levels

Table 4.4. Power-On-Reset Voltage Levels*

Symbol

Device

Parameter

Min

Max

Unit

V

PORUP

iCE40LP384

Power-On-Reset ramp-up trip point (band gap

based circuit monitoring VCC, VCCIO_2, VCC_SPI

and VPP_2V5)

V

CC

0.67

0.99

V

0.70

1.59

V

V

CC_SPI

0.70

1.59

V

V

PP_2V5

0.70

1.59

V

iCE40LP640,

iCE40LP/HX1K,

iCE40LP/HX4K,

iCE40LP/HX8K

Power-On-Reset ramp-up trip point (band gap

based circuit monitoring VCC, VCCIO_2, VCC_SPI

and VPP_2V5)

V

CC

0.55

0.75

V

0.86

1.29

V

V

CC_SPI

0.86

1.29

V

V

PP_2V5

0.86

1.33

V

iCE40LP384

Power-On-Reset ramp-down trip point (band gap

based circuit monitoring VCC, VCCIO_2, VCC_SPI

and VPP_2V5)

V

CC

—

0.64

V

—

1.59

V

V

CC_SPI

—

1.59

V

V

PP_2V5

—

1.59

V

iCE40LP640,

iCE40LP/HX1K,

iCE40LP/HX4K,

iCE40LP/HX8K

Power-On-Reset ramp-down trip point (band gap

based circuit monitoring VCC, VCCIO_2, VCC_SPI

and VPP_2V5)

V

CC

—

0.75

V

—

1.29

V

V

CC_SPI

—

1.29

V

V

PP_2V5

—

1.33

V

*Note: These POR trip points are only provided for guidance. Device operation is only characterized for power supply voltages

specified under recommended operating conditions.

4.5. ESD Performance

Please refer to the iCE40 Product Family Qualification Summary for complete qualification data, including ESD performance.