iCE40 LP/HX Family

Data Sheet

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4

FPGA-DS-02029-3.5

Tables

Table 2.1. iCE40 LP/HX Family Selection Guide ....................................................................................................................7

Table 3.1. Logic Cell Signal Descriptions .............................................................................................................................10

Table 3.2. Global Buffer (GBUF) Connections to Programmable Logic Blocks....................................................................10

Table 3.3. PLL Signal Descriptions.......................................................................................................................................12

Table 3.4. sysMEM Block Configurations*..........................................................................................................................13

Table 3.5. EBR Signal Descriptions ......................................................................................................................................14

Table 3.6. PIO Signal List .....................................................................................................................................................16

Table 3.7. Supported Input Standards ................................................................................................................................17

Table 3.8. Supported Output Standards .............................................................................................................................17

Table 3.9. Power Saving Features Description....................................................................................................................18

Table 4.1. Absolute Maximum Ratings* .............................................................................................................................19

Table 4.2. Recommended Operating Conditions1 ..............................................................................................................19

Table 4.3. Power Supply Ramp Rates* ...............................................................................................................................20

Table 4.4. Power-On-Reset Voltage Levels* .......................................................................................................................20

Table 4.5. DC Electrical Characteristics...............................................................................................................................21

Table 4.6. Supply Current– LP Devices1, 2, 3, 4.......................................................................................................................21

Table 4.7. Supply Current– HX Devices1, 2, 3, 4......................................................................................................................22

Table 4.8. Programming NVCM Supply Current – LP Devices1, 2, 3, 4....................................................................................22

Table 4.9. Programming NVCM Supply Current – HX Devices1, 2, 3, 4 ...................................................................................23

Table 4.10. Peak Startup Supply Current – LP Devices .......................................................................................................23

Table 4.11. Peak Startup Supply Current – HX Devices ......................................................................................................24

Table 4.12. sysI/O Recommended Operating Conditions...................................................................................................24

Table 4.13. sysI/O Single-Ended DC Electrical Characteristics ............................................................................................24

Table 4.14. LVDS25 .............................................................................................................................................................25

Table 4.15. subLVDS............................................................................................................................................................25

Table 4.16. LVDS25E DC Conditions....................................................................................................................................26

Table 4.17. subLVDSE DC Conditions ..................................................................................................................................27

Table 4.18. Pin-to-Pin Performance (LVCMOS25) – LP Devices..........................................................................................28

Table 4.19. Register-to-Register Performance – LP Devices...............................................................................................28

Table 4.20. Pin-to-Pin Performance (LVCMOS25) – HX Devices .........................................................................................28

Table 4.21. Register-to-Register Performance – HX Devices ..............................................................................................29

Table 4.22. Register-to-Register Performance1 ..................................................................................................................29

Table 4.23. Timing Adders – LP Devices*............................................................................................................................30

Table 4.24. Timing Adders – HX Devices*...........................................................................................................................30

Table 4.25. External Switching Characteristics – LP Devices1, 2...........................................................................................31

Table 4.26. External Switching Characteristics – HX Devices1, 2..........................................................................................33

Table 4.27. sysClock PLL Timing..........................................................................................................................................34

Table 4.28. SPI Master or NVCM Configuration Time1, 2.....................................................................................................35

Table 4.29. sysCONFIG Port Timing Specifications1 ............................................................................................................36

Table 4.30. Test Fixture Required Components, Non-Terminated Interfaces ....................................................................37