iCE40 LP/HX Family

Data Sheet

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FPGA-DS-02029-3.5

13

Table 3.4. sysMEM Block Configurations*

Block RAM

Configuration

Block RAM

Configuration

and Size

WADDR Port

Size (Bits)

WDATA Port

Size (Bits)

RADDR Port

Size (Bits)

RDATA Port

Size (Bits)

MASK Port

Size (Bits)

SB_RAM256x16

SB_RAM256x16NR

SB_RAM256x16NW

SB_RAM256x16NRNW

256 x 16 (4 k)

8 [7:0]

16 [15:0]

8 [7:0]

16 [15:0]

16 [15:0]

SB_RAM512x8

SB_RAM512x8NR

SB_RAM512x8NW

SB_RAM512x8NRNW

512 x 8 (4 k)

9 [8:0]

8 [7:0]

9 [8:0]

8 [7:0]

No Mask Port

SB_RAM1024x4

SB_RAM1024x4NR

SB_RAM1024x4NW

SB_RAM1024x4NRNW

1024 x 4 (4 k)

10 [9:0]

4 [3:0]

10 [9:0]

4 [3:0]

No Mask Port

SB_RAM2048x2

SB_RAM2048x2NR

SB_RAM2048x2NW

SB_RAM2048x2NRNW

2048 x 2 (4 k)

11 [10:0]

2 [1:0]

11 [10:0]

2 [1:0]

No Mask Port

*Note: For iCE40 LP/HX EBR primitives with a negative-edged Read or Write clock, the base primitive name is appended with a ‘N’

and a ‘R’ or W depending on the clock that is affected.

3.1.5.2. RAM Initialization and ROM Operation

If desired, the contents of the RAM can be pre-loaded during device configuration.

By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block

can also be utilized as a ROM.

Note that the sysMEM Embedded Block RAM Memory address 0 cannot be initialized.

3.1.5.3. Memory Cascading

Larger and deeper blocks of RAM can be created using multiple EBR sysMEM Blocks.

3.1.5.4. RAM4k Block

the input data and addresses for the ports are registered at the input of the memory array.

WCLK

WE

RE

WCLKE

RCLKE

RCLK

WDATA[15:0]

RDATA[15:0]

MASK[15:0]

WADDR[7:0]

RADDR[7:0]

Write Port

Read Port

RAM4K

RAM Block

(256 x 16)

Figure 3.4. sysMEM Memory Primitives