iCE40 LP/HX Family

Data Sheet

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FPGA-DS-02029-3.5

Table 3.5 lists the EBR signals.

Table 3.5. EBR Signal Descriptions

Signal Name

Direction

Description

WDATA[15:0]

Input

Write Data input.

MASK[15:0]

Input

Masks write operations for individual data bit-lines.

0 – Write bit

1 – Do not write bit

WADDR[7:0]

Input

Write Address input. Selects one of 256 possible RAM locations.

WE

Input

Write Enable input.

WCLKE

Input

Write Clock Enable input.

WCLK

Input

Write Clock input. Default rising-edge, but with falling-edge option.

RDATA[15:0]

Output

Read Data output.

RADDR[7:0]

Input

Read Address input. Selects one of 256 possible RAM locations.

RE

Input

Read Enable input.

RCLKE

Input

Read Clock Enable input.

RCLK

Input

Read Clock input. Default rising-edge, but with falling-edge option.

For further information on the sysMEM EBR block, refer to Memory Usage Guide for iCE40 Devices (TN1250).

3.1.6. sysI/O

Buffer Banks

iCE40 LP/HX devices have up to four I/O banks with independent V

CC_SPI

for the SPI I/Os.

Programmable I/O (PIO)

The programmable logic associated with an I/O is called a PIO. The individual PIOs are connected to their respective

sysI/O buffers and pads. The PIOs are placed on the top and bottom of the devices.