iCE40 LP/HX Family

Data Sheet

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FPGA-DS-02029-3.5

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3.1.3.1. Global Hi-Z Control

The global high-impedance control signal, GHIZ, connects to all I/O pins on the iCE40 LP/HX device. This GHIZ signal is

automatically asserted throughout the configuration process, forcing all user I/O pins into their high-impedance state.

3.1.3.2. Global Reset Control

The global reset control signal connects to all PLB and PIO flip-flops on the iCE40 LP/HX device. The global reset signal is

automatically asserted throughout the configuration process, forcing all flip-flops to their defined wake-up state. For

PLB flip-flops, the wake-up state is always reset, regardless of the PLB flip-flop primitive used in the application.

3.1.4. sysCLOCK Phase Locked Loops (PLLs)

The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The iCE40 LP/HX devices have one sysCLOCK PLL.

REFERENCECLK is the reference frequency input to the PLL and its source can come from an external I/O pin, the

internal Oscillator Generators from internal routing. EXTFEEDBACK is the feedback signal to the PLL which can come

from internal routing or an external I/O pin. The feedback divider is used to multiply the reference frequency and thus

synthesize a higher frequency clock output.

The PLLOUT output has an output divider, thus allowing the PLL to generate different frequencies for each output. The

output divider can have a value from 1 to 64 (in increments of 2X). The PLLOUT outputs can all be used to drive the

iCE40 LP/HX global clock network directly or general purpose routing resources can be used.

The LOCK signal is asserted when the PLL determines it has achieved lock and de-asserted if a loss of lock is detected. A

block diagram of the PLL is shown in Figure 3.3.

The timing of the device registers can be optimized by programming a phase shift into the PLLOUT output clock which

will advance or delay the output clock with reference to the REFERENCECLK clock. This phase shift can be either

programmed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after a phase

adjustment on the output used as the feedback source and not relock until the tLOCK parameter has been satisfied.

There is an additional feature in the iCE40 LP/HX PLL. There are two FPGA controlled inputs, SCLK and SDI, that allows

the user logic to serially shift in data thru SDI, clocked by SCLK clock. The data shifted in would change the configuration

settings of the PLL. This feature allows the PLL to be time multiplexed for different functions, with different clock rates.

After the data is shifted in, you would simply pulse the RESET input of the PLL block, and the PLL will re-lock with the

new settings. For more details, refer to iCE40 sysCLOCK PLL Design and Usage Guide (TN1251).

Input

Divider

DIVR

Low-Pass

Filter

Voltage

Controlled

Oscillator

(VCO)

VCO

Divider

DIVQ

Feedback

Divider

DIVF

RANGE

Phase

Detector

Feedback_Path

Fine Delay

Adjustment

Feedback

Phase

Shifter

LATCHINPU TVALUE

REFERENCECLK

DYNAMICDELAY[7:0]

BYPASS

RESET

EXTFEEDBACK

PLLOUTCORE

PLLOUTGLOBAL

LOCK

BYPASS

Low Powermode

SIMPLE

EXTERNAL

GNDPLL

Fine Delay

Adjustment

Output Port

SCLK

SDI

Figure 3.3. PLL Diagram