iCE40 LP/HX Family

Data Sheet

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FPGA-DS-02029-3.5

Table 3.1. Logic Cell Signal Descriptions

Function

Type

Signal Name

Description

Input

Data signal

I0, I1, I2, I3

Inputs to LUT4

Input

Control signal

Enable

Clock enable shared by all LCs in the PLB

Input

Control signal

Set/Reset*

Asynchronous or synchronous local set/reset shared by

all LCs in the PLB.

Input

Control signal

Clock

Clock one of the eight Global Buffers, or from the

general-purpose interconnects fabric shared by all LCs

in the PLB.

Input

Inter-PLB signal

FCIN

Fast carry in

Output

Data signals

O

LUT4 or registered output

Output

Inter-PFU signal

FCOUT

Fast carry out

*Note

: If Set/Reset is not used, then the flip-flop is never set/reset, except when cleared immediately after configuration.

3.1.2. Routing

There are many resources provided in the iCE40 LP/HX devices to route signals individually with related control signals.

The routing resources consist of switching circuitry, buffers, and metal interconnect (routing) segments.

The inter-PLB connections are made with three different types of routing resources: Adjacent (spans two PLBs), x4

(spans five PLBs) and x12 (spans thirteen PLBs). The Adjacent, x4, and x12 connections provide fast and efficient

connections in the diagonal, horizontal and vertical directions.

The design tool takes the output of the synthesis tool and places and routes the design.

3.1.3. Clock/Control Distribution Network

Each iCE40 LP/HX device has eight global inputs, two pins on each side of the device. Note that not all GBINs are

available in all packages.

These global inputs can be used as high fanout nets, clock, reset or enable signals. The dedicated global pins are

identified as GBIN[7:0] and the global buffers are identified as-GBUF[7:0]. These eight inputs may be used as general

purpose I/O if they are not used to drive the clock nets. Global buffer GBUF7 in I/O Bank 3 also provides an optional

direct LVDS25 or subLVDS differential clock input.

Table 3.2 lists the connections between a specific global buffer and the inputs on a PLB. All global buffers optionally

connect to the PLB CLK input. Any four of the eight global buffers can drive logic inputs to a PLB. Even-numbered global

buffers optionally drive the Set/Reset input to a PLB. Similarly, odd-numbered buffers optionally drive the PLB clock-

enable input.

Table 3.2. Global Buffer (GBUF) Connections to Programmable Logic Blocks

Global Buffer

LUT Inputs

Clock

Reset

Clock Enable

GBUF0

Yes, any 4 of 8 GBUF

Inputs

Yes

Yes

—

GBUF1

Yes

—

Yes

GBUF2

Yes

Yes

—

GBUF3

Yes

—

Yes

GBUF4

Yes

Yes

—

GBUF5

Yes

—

Yes

GBUF6

Yes

Yes

—

GBUF7

Yes

—

Yes

The maximum frequency for the global buffers are listed in the External Switching Characteristics tables in this

document.