iCE40 LP/HX Family

Data Sheet

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FPGA-DS-02029-3.5

Table 3.3. PLL Signal Descriptions

Signal Name

Direction

Description

REFERENCECLK

Input

Input reference clock

BYPASS

Input

The BYPASS control selects which clock signal connects to the PLLOUT output.

0 – PLL generated signal

1 – REFERENCECLK

EXTFEEDBACK

Input

External feedback input to PLL. Enabled when the FEEDBACK_PATH attribute is set

to EXTERNAL.

DYNAMICDELAY[7:0]

Input

Fine delay adjustment control inputs. Enabled when DELAY_ADJUSTMENT_MODE

is set to DYNAMIC.

LATCHINPUTVALUE

Input

When enabled, puts the PLL into low-power mode; PLL output is held static at the

last input clock value. Set ENABLE ICEGATE_PORTA and PORTB to 1 to enable.

PLLOUTGLOBAL

Output

Output from the Phase-Locked Loop (PLL). Drives a global clock network on the

FPGA. The port has optimal connections to global clock buffers GBUF4 and GBUF5.

PLLOUTCORE

Output

Output clock generated by the PLL, drives regular FPGA routing. The frequency

generated on this output is the same as the frequency of the clock signal generated

on the PLLOUTLGOBAL port.

LOCK

Output

When High, indicates that the PLL output is phase aligned or locked to the input

reference clock.

RESET

Input

Active low reset.

SCLK

Input

Input, Serial Clock used for re-programming PLL settings.

SDI

Input

Input, Serial Data used for re-programming PLL settings.

3.1.5. sysMEM Embedded Block RAM Memory

Larger iCE40 LP/HX device includes multiple high-speed synchronous sysMEM Embedded Block RAMs (EBRs), each

4 kbit in size. This memory can be used for a wide variety of purposes including data buffering and FIFO.

3.1.5.1. sysMEM Memory Block

The sysMEM block can implement single port, pseudo dual port, or FIFO memories with programmable logic resources.

Each block can be used in a variety of depths and widths as listed in Table 3.4.