iCE40 LP/HX Family

Data Sheet

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42

FPGA-DS-02029-3.5

iCE40HX4K

iCE40HX8K

BG121

CB132

TQ144

BG121

CB132

CM225

CT256

General Purpose I/O per Bank

Bank 0

23

24

27

23

24

46

52

Bank 1

21

25

29

21

25

42

52

Bank 2

19

18

19

19

18

40

46

Bank 3

26

24

28

26

24

46

52

Configuration

4

4

4

4

4

4

4

Total General Purpose Single Ended

I/O

93

95

107

93

95

178

206

High Current Outputs per Bank

Bank 0

0

0

0

0

0

0

0

Bank 1

0

0

0

0

0

0

0

Bank 2

0

0

0

0

0

0

0

Bank 3

0

0

0

0

0

0

0

Total Differential Inputs

0

0

0

0

0

0

0

Differential Inputs per Bank

Bank 0

0

0

0

0

0

0

0

Bank 1

0

0

0

0

0

0

0

Bank 2

0

0

0

0

0

0

0

Bank 3

13

12

14

13

12

23

26

Total Differential Inputs

13

12

14

13

12

23

26

Dedicated Inputs per Bank

Bank 0

0

0

0

0

0

0

0

Bank 1

0

0

0

0

0

0

0

Bank 2

2

2

2

2

2

2

2

Bank 3

0

0

0

0

0

0

0

Configuration

0

0

0

0

0

0

0

Total Dedicated Inputs

2

2

2

2

2

2

2

Vccio Pins

Bank 0

1

2

2

1

2

3

4

Bank 1

1

2

2

1

2

3

4

Bank 2

1

2

2

1

2

3

4

Bank 3

2

3

2

2

3

4

4

4

5

4

4

5

8

6

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

2

2

2

2

2

2

2

GND

12

15

11

12

15

18

20

NC

0

0

6

0

0

0

0

Total Count of Bonded Pins

121

132

144

121

132

225

256