iCE40 LP/HX Family

Data Sheet

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FPGA-DS-02029-3.5

3.1.8. Non-Volatile Configuration Memory

All iCE40 LP/HX devices provide a Non-Volatile Configuration Memory (NVCM) block which can be used to configure the

device.

For more information on the NVCM, refer to iCE40 Programming and Configuration (FPGA-TN-02001).

3.1.9. Power On Reset

configuration) voltage levels. It then triggers download from the on-chip NVCM or external Flash memory after

reaching the power-up levels specified in the Power-On-Reset Voltage table in the DC and Switching Characteristics

section of this data sheet. Before and during configuration, the I/Os are held in tri-state. I/Os are released to user

functionality once the device has finished configuration.

3.2. Programming and Configuration

This section describes the programming and configuration of the iCE40 LP/HX family.

Device Programming

The NVCM memory can be programmed through the SPI port.

Device Configuration

There are various ways to configure the Configuration RAM (CRAM) including:



Internal NVCM Download



From an SPI Flash (Master SPI mode)



System microprocessor to drive a Serial Slave SPI port (SSPI mode)

The image to configure the CRAM can be selected by the user on power up (Cold Boot) or once powered up (Warm

Boot).

For more details on configuring the iCE40 LP/HX device, refer to iCE40 Programming and Configuration (FPGA-TN-

3.2.1. Power Saving Options

iCE40 LP/HX devices are available in two options for maximum flexibility: LP and HX devices. The LP devices have ultra

low static and dynamic power consumption. HX devices are designed to provide high performance. Both the LP and

iCE40 LP/HX devices feature iCEGate and PLL low power mode to allow users to meet the static and dynamic power

requirements of their applications. While these features are available in both device types, these features are mainly

intended for use with iCE40 LP devices to manage power consumption.

Table 3.9. Power Saving Features Description

Device Subsystem

Feature Description

PLL

When LATCHINPUTVALUE is enabled, puts the PLL into low-power mode; PLL output held static at last

input clock value.

iCEGate

To save power, the optional iCEGate latch can selectively freeze the state of individual, non-registered

inputs within an I/O bank. Registered inputs are effectively frozen by their associated clock or clock-

enable control.