iCE40 LP/HX Family

Data Sheet

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FPGA-DS-02029-3.5

25

4.15. sysI/O Differential Electrical Characteristics

The LVDS25E/subLVDSE differential output buffers are available on all banks but the LVDS/subLVDS input buffers are

only available on Bank 3 of iCE40 LP/HX devices.

4.15.1. LVDS25

Over recommended operating conditions.

Table 4.14. LVDS25

Parameter

Symbol

Parameter Description

Test

Conditions

Min.

Typ.

Max.

Units

Input Voltage

0

—

2.5

V

Differential Input Threshold

—

250

350

450

mV

Input Common Mode

Voltage

V

Input Current

Power on

—

—

±10

µA

*Note: Typical

4.15.2. subLVDS

Over recommended operating conditions.

Table 4.15. subLVDS

Parameter

Symbol

Parameter Description

Test

Conditions

Min.

Typ.

Max.

Units

Input Voltage

0

—

1.8

V

Differential Input Threshold

—

100

150

200

mV

Input Common Mode

Voltage

0.25

0.25

V

Input Current

Power on

—

—

±10

µA

*Note: Typical