LTM4677 datasheet(39/110 Pages) AD

39 / 110 page

LTC3888-1

Rev. 0

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OPERATION

Serial Bus Addressing

The LTC3888-1 supports four types of serial bus

addressing:

• Global Bus Addressing

• Power Rail Addressing

• Individual Device Addressing

• Page+ Master Channel Addressing

Global addressing provides a means for the bus master

to communicate with all LTC3888-1 devices on the bus

simultaneously. The LTC3888-1 global addresses of 0x5A

and 0x5B cannot be changed or disabled. Commands sent

to address 0x5A are applied to both master channels as

if the PAGE command were set to 0xFF. Global address

0x5B is paged, allowing channel-specific control of all

LTC3888-1 devices on the bus. Other ADI device types

may respond at one or both of these global addresses.

Reading from global addresses is strongly discouraged.

Rail addressing provides a means for the bus master to

simultaneously communicate with all master channels

connected together to produce a single output voltage

(PolyPhase). While similar to global addressing, the rail

address can be dynamically assigned with the paged

MFR_RAIL_ADDRESS command, allowing for any logi-

cal grouping of channels that might be required for reli-

able system control. Reading from rail addresses is also

strongly discouraged.

Device addressing is the most common means used by

a bus master to communicate with an LTC3888-1. The

value of the device address is set by the combination of

ASEL0/ASEL1 pin programming and the MFR_ADDRESS

command. Refer to the previous section on Resistor

Configuration Pins for details.

Direct, individual channel addressing (Page+) allows

the bus master to communicate directly with a specific

LTC3888-1 PWM master channel without first using a

PAGE command. Refer to the PAGE_PLUS commands

for additional details.

Use of any of the four types of addressing requires

careful planning to avoid address-related bus conflicts.

Communication to LTC3888-1 devices at global and rail

addresses should be limited to command write operations.

Serial Bus Timeout

The LTC3888-1 implements a timeout feature to avoid

hanging the serial interface. The data packet timer

begins running at the first START event before the SLAVE

ADDRESS write byte and ends with the STOP bit. Packet

transmission must be completed before the timer expires,

or the LTC3888-1 will tri-state the bus and ignore all mes-

sage data. The data packet includes the SLAVE ADDRESS

byte, COMMAND CODE byte, repeated START and SLAVE

ADDRESS byte (if a read operation), all ACKNOWLEDGE

and flow control bits (R/W) and all data bytes.

The packet timer is typically set to 30ms. If bit 3 of MFR_

CONFIG_ALL is set, this period is extended to 255ms. The

LTC3888-1 automatically allows a packet transmission

time of 255ms for MFR_FAULT_LOG block reads regard-

less of the setting of this bit. In no circumstances will

the timeout period be less than the tTIMEOUT specification

(25ms minimum).

The LTC3888-1 supports a PMBus frequency range of

10kHz to 400kHz.

Serial Communication Errors

The LTC3888-1 supports the optional PMBus packet

error checking protocol. This protocol appends a packet

error code (PEC) to the end of applicable message trans-

fers to improve communication reliability. The PEC is a

CRC-8 error-checking byte calculated by the bus device

sending the last data byte. Refer to SMBus specification

1.2 or higher for additional implementation details. All

LTC3888-1 read operations will return a valid PEC if the

bus master requests it. If bit 2 in the MFR_CONFIG_ALL

command is set, the IC will not act in response to a bus

write operation unless a valid PEC is also received from

the host.

PEC errors on command writes, attempts to access

unsupported commands, or writing invalid data to sup-

ported commands all cause the LTC3888-1 to generate a

CML fault. The CML bit is then set in the STATUS_BYTE

and STATUS_WORD commands, and the appropriate bit

is set in the STATUS_CML command.

LTM4677 Datasheet(PDF) 39 Page - Analog Devices

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