LTM4677 datasheet(45/110 Pages) AD

45 / 110 page

LTC3888-1

Rev. 0

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EFFICIENCY CONSIDERATIONS

Normally, one of the primary goals of any LTC3888-1

application will be to obtain the highest practical conver-

sion efficiency. The efficiency of a switching regulator is

equal to the output power divided by the input power. It is

often useful to analyze individual losses to determine what

is limiting the efficiency and to ascertain which change

would produce the most improvement. Balancing or limit-

ing these individual losses plays a dominant role in the

component selection process outlined over the next few

sections.

Percent efficiency can be expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + …)

where L1, L2, et al, are the individual losses as a percent-

age of input power: 100 • PLn /PIN.

Although all dissipative elements in the system produce

losses, four main sources usually account for most of

the losses in LTC3888-1 applications: IC supply current,

I2R losses, topside power MOSFET transition losses and

total gate drive current.

1. The LTC3888-1 IC supply current is a DC value given

in the Electrical Characteristics table. The absolute

loss created by the IC itself is approximately this cur-

rent times the VIN supply voltage. IC supply current

typically results in a small loss (<0.1%).

2. I2R losses occur mainly in the DC resistances of the

selected power stage, inductor, PCB routing, and

input and output capacitor ESR. It is crucial that care-

ful attention is paid to the layout of the power path on

the PCB to minimize that resistance. In a 2-phase 1.2V

system, 1mΩ of PCB resistance at the output costs

5% in efficiency with the output running at 60A.

3. Transition losses apply only to the selected power

stage and normally do not become significant until

operating above 12V.

4. Gate drive current is equal to the sum of the top and

bottom MOSFET gate charges multiplied by the fre-

quency of operation. These charges are based on

internal power stage design and are normally included

in overall efficiency (or power loss) numbers provded

by the manufacturer at a given operating condtion.

APPLICATIONS INFORMATION

Other sources of loss include internal body or external

Schottky diode conduction during the power stage FET

driver non-overlap time, as well as inductor core losses.

These latter categories generally account for less than 2%

total additional loss.

POWER STAGE SELECTION AND INTERFACE

The LTC3888-1 operates with power stages that provide

a voltage or current monitor of the output current they

sense. As a minimum, these stages must also accept

3.3V-compatible three-state PWM input control. Other

features such as PWM input off-state biasing, power

stage temperature monitoring, fault detection and indi-

cation, and UVLO protection are optional. Examples of

these kinds of devices include the TDA21470, IR35411

and FDM3170.

The LTC3888-1 ISENSE pins are high impedance inputs to

internal interface circuits and the monitor ADC, both using

a common mode of IREF (1.6V). Maximum instantaneous

differential current sense input relative to IREF is 525mV,

and maximum DC input differential is 400mV. These

inputs must be properly connected in the application at

all times. While not strictly required, it is recommended

to short ISENSE to IREF on PWM channels disabled by

MFR_PWM_CONFIG_LTC3888-1 master/slave setting.

As shown in Figure 22 and Figure 23, the LTC3888-1 is

designed to interface to power stages that provide either

a current or voltage analog of sensed output current.

The LTC3888-1 IREF output should be used to provide

the common mode voltage for this output current moni-

tor, with some bypass located adjacent to each power

stage and returned to GND (IC paddle). The LTC3888-1

is designed to work best when the power stage output

current monitor is scaled to provide between 3mV/A and

10mV/A to its ISENSE input. This scaling must be identical

for all phases on a rail. For most power stages providing

a voltage-mode monitor, no additional external scaling

components are required.

Some of these power stages require the controller to pro-

vide a PWM pulse with a minimum width. The LTC3888-1

can be configured to accommodate this requirement by

setting bit 1 of MFR_PWM_MODE_LTC3888-1.

LTM4677 Datasheet(PDF) 45 Page - Analog Devices

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