LTM4677 datasheet(13/110 Pages) AD

13 / 110 page

LTC3888-1

Rev. 0

For more information www.analog.com

PIN FUNCTIONS

PWM

n (Pin 1, 2, 5, 42, 45, 46, 49, 50): PWM Control

Outputs. These eight pins provide 3.3V three-state PWM

switching control for each phase. Leave these pins open

if not used.

ISENSEn (Pin 3, 4, 43, 44, 47, 48, 51, 52): Current Sense

Inputs. These eight inputs connect to the current moni-

tor outputs of DrMOS devices. Short these pins to IREF

if not used.

VSENSE0–/VSENSE1– (Pin 6/Pin 41): Differential Amplifier

and ADC Output Voltage Sense Negative Inputs. Short

these pins to GND if not used.

VSENSE0+/VSENSE1+ (Pin 7/Pin 40): Differential Amplifier

and ADC Output Voltage Sense Positive Inputs. Short

these pins to VSENSE– if not used.

TSNS0/TSNS1 (Pin 8/Pin 39): External Temperature

Sense Inputs. Connect these pins to the shared tempera-

ture/fault bus of DrMOS devices, otherwise refer to the

Applications Information section for more detail.

VDR_MON (Pin 8): External Gate Drive Voltage Sense

Input. This pin can be programmed to monitor the gate

drive voltage the system is providing to external DrMOS

power stages. Refer to MFR_CHAN_CONFIG command

details.

ITH0/ITH1 (Pin 9/Pin 38): PWM Current Control Threshold

and Loop Compensation Nodes. Peak current increases

with ITH voltage. Attach a low ESR capacitor between

these pins and GND for adequate loop compensation.

Refer to the Applications Information section for more

details.

ITHR0/ITHR1 (Pin 10/Pin 37): Loop Compensation Nodes.

Attach a low ESR capacitor between these pins and GND

for adequate loop compensation. Refer to the Applications

Information section for more details.

DAOUT0/DAOUT1 (Pin 11/Pin 36): Differential Amplifier

Outputs. DAOUT0/1 provide a voltage equal to the dif-

ference between VSENSE+ and VSENSE– for that channel,

referenced to GND (paddle). Leave these pins open if not

used.

VFB0/VFB1 (Pin 12/Pin 35): Error Amplifier Inverting Input.

The PWM control loop regulates this voltage when the

output rail is on.

PGOOD0/PGOOD1 (Pin 13/Pin 34): Power Good Indicator

Open-Drain Outputs. These outputs are driven low through

an 80μs filter when the respective channel output is below

its programmed UV fault limit or above its programmed

OV fault limit. If used, a pull-up resistor is required in the

application.

CLKOUT (Pin 13): Expansion Clock Output. This output

provides a phase expansion clock to a second LTC3888-1

if bit 3 of MFR_PWM_ CONFIG_LTC3888-1 is set. If used,

a pull-up resistor is required. Minimize the capacitance

on this line to ensure its time constant is fast enough for

the application.

SYNC (Pin 14): External Clock Synchronization Input and

Open-Drain Output. If desired, an external clock can be

applied to this pin to synchronize the internal PWM chan-

nels. Otherwise this pin can pull to ground at the selected

PWM switching frequency with a 500ns pulse width. A

pull-up resistor to 3.3V is required if SYNC is provided by

the LTC3888-1. Minimize the capacitance on this line to

ensure its time constant is fast enough for the application.

SCL (Pin 15): Serial Bus Clock Input and Open-Drain

Output. SCL functions as an output only if clock stretch-

ing is enabled. A pull-up resistor to the bus supply is

required in the application.

SDA (Pin 16): Serial Bus Data Input and Open-Drain

Output. A pull-up resistor to the bus supply is required

in the application.

ALERT (Pin 17): Open-Drain Status Output. This pin may

be connected to the system SMBALERT# wire-AND inter-

rupt signal. A pull-up resistor to the bus supply is required

in the application. This pin should be left open if not used.

FAULT0/FAULT1 (Pin 18/Pin 19): Programmable Digital

Inputs and Open-Drain Outputs for Fault Sharing. These

pins are used for channel-to-channel fault communication

and propagation. A pull-up resistor to 3.3V is required in

the application.

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