LTM4677 datasheet(19/110 Pages) AD

19 / 110 page

LTC3888-1

Rev. 0

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OPERATION

The PMBus interface provides access to important power

management data during system operation including:

• Average Input Voltage

• Average Output Voltages

• Average Output Currents

• PWM Operating Frequency

• Internal Device Temperature

• External Sensed Temperatures

• Warning and Fault Status, Including Input and Output

Undervoltage and Overvoltage

The LTC3888-1 supports four PMBus bus addressing

schemes to access the individual PWM voltage loops

separately or jointly.

Fault reporting and system response behavior are fully

configurable. The two status outputs (FAULT0, FAULT1)

can be controlled independently. A separate ALERT pin

also provides a maskable SMBALERT#. Fault responses

for each channel may be individually programmed,

depending on the fault type. PMBus status commands

allow fault reporting over the serial bus to identify a spe-

cific fault event.

MAIN CONTROL LOOP

The LTC3888-1 utilizes constant frequency current mode

control with trailing-edge modulation. The main con-

trol loop used for each master channel is illustrated in

Figure 1. During normal operation the top MOSFET in

the external power stage (power switch) driving choke

L1 is commanded on when the clock phase for that mas-

ter sets the RS latch, unless the main PWM compara-

tor ICMP indicates there is already too much current in

L1. In that case no additional energy is delivered to the

choke during that cycle (PWM output remains low, cycle

skipped). Otherwise the latch is reset and power switch

commanded off later in the cycle by the PWM compara-

tor. Sensed output current is provided from the external

power stage at the ISENSE pin. The point in the PWM cycle

at which ICMP resets the RS latch is controlled by the

ITH voltage provided by the output of error amplifier EA,

including internal slope compensation for stable opera-

tion regardless of duty cycle. ln steady state, ITH adjusts

the PWM duty cycle to match the VFB voltage to the EA

positive terminal voltage.

The positive terminal of EA is connected to the output of a

12-bit DAC with values ranging from 0V to approximately

1.22V. The DAC value is determined by command values

retrieved from internal EEPROM or by a combination of

PMBus commands to synthesize the desired output volt-

age. The factory default EEPROM sets the value of this

DAC output to 400mV. The EA then regulates the output

voltage based on the ratio of external resistors R1 and R2.

If load current increases, VSENSE+ and thus VFB will droop

slightly, VFB with respect to the 12-bit DAC output. This

causes the ITH voltage to increase until the average induc-

tor current matches the new load current and the desired

output voltage is restored. ITH is monitored to provide pro-

grammable over-current protection with comparator ILIM.

When the top MOSFET is commanded off by the PWM

output, the bottom MOSFET is commanded on. The

LTC3888-1 operates in continuous conduction mode

(CCM), so the bottom MOSFET stays on until the PWM

clock next turns on the top MOSFET or the rail is com-

manded off.

POWER-UP AND INITIALIZATION

The LTC3888-1 is designed to provide standalone supply

sequencing with controlled turn-on and turn-off functions.

It operates from a VIN supply of 4.5V to 26.5V while three

on-chip linear regulators generate internal 2.5V, 3.3V and

5.2V. If VIN is below 6V, the VIN and INTVCC pins must

be shorted together and limited to a maximum operat-

ing voltage of 5.5V. Controller configuration is reset by

the internal UVLO threshold, where INTVCC must be at

or above 4.45V, VDD33 must be at or above 3.1V and

the internal 2.5V supply must be within about 20% of its

regulated value. VIN must simply be high enough for the

LDO outputs to reach these voltages. At that point the

internal microcontroller begins initialization. A RESTORE_

USER_ALL or MFR_RESET forces this same initialization.

The LTC3888-1 features an internal RAM built-in self-test

(BIST) that runs during initialization. Should RAM BIST

fail, the following steps are taken.

LTM4677 Datasheet(PDF) 19 Page - Analog Devices

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