LTM4677 datasheet(46/110 Pages) AD

46 / 110 page

LTC3888-1

Rev. 0

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APPLICATIONS INFORMATION

The LTC3888-1 TSNS pins interface directly to the wire-

OR shared TEMP/FAULT bus found on most power stages

offering output current monitor. When all phases are fault-

free, the voltage on this bus indicates the highest power

stage temperature on the rail. The internal monitor ADC

converts this voltage, and the computed temperature

value is returned by the paged READ_TEMPERATURE_1

telemetry command. The slope of the external tempera-

ture sensor can be modified to fit the selected power stage

using the coefficient stored in MFR_TEMP_1_GAIN. The

offset of the external temperature sense can be adjusted

by MFR_TEMP_1_OFFSET, which designates the bus volt-

age indicating 0°C.

The LTC3888-1 also recognizes indicated power stage

fault conditions on the shared TEMP/FAULT bus. This

includes support for optional power stage UV indication

when enabled with bit 0 of MFR_PWM_MODE_LTC3888-

1. These events are reported through standard PMBus

status registers for improved system state observation

by the bus host as shown in Table 8. Refer to previ-

ous Operation section discussions on Hardwired PWM

Response to Power Stage Faults and Status Registers

and ALERT Masking for additional details.

Figure 22. Interface to Current-Mode Output Current Sense

Figure 23. Interface to Voltage-Mode Output Current Sense

SCALE TO

ACHIEVE

~5mV/A

TO OTHER

POWER

STAGES

IMON

REFIN

EXTERNAL POWER

STAGE

388812 F22

ISENSE

IREF

GND

LTC3888-1

0.47µF

TO OTHER

POWER

STAGES

IOUT

REFIN

EXTERNAL POWER

STAGE

388812 F23

ISENSE

IREF

GND

LTC3888-1

0.47µF

Table 8. Special LTC3888-1 Status Indications1

CONDITION

INDICATED

PAGED

MFR_PADS_LTC3888-15

STATUS_VOUT

BIT 7

(VOUT_OV FAULT)

STATUS_VOUT

BIT 4

(VOUT_UV FAULT)

STATUS_IOUT

BIT 3

CH0/1 DrMOS

READY

BIT 14/15

VOUT OV

•

VOUT UV

•

VSENSE+ OPEN2,3

•

Power Stage UV

(TSNS)4 or VDR

Monitor UV

•

(IFF CH Set to Run)

Power Stage Fault6

•

1With the exception of VSENSE+ Open, all VOUT_OV Fault conditions are handled by VOUT_OV_FAULT_RESPONSE, which is immediate off with no retry,

and a VOUT_UV fault condition is handled by VOUT_UV_FAULT_RESPONSE.

2Both VSENSE+ lines are tested each time the LTC3888-1 powers up or resets. The response of the LTC3888-1 for any open VSENSE+ line is to disable all

outputs. A detected open line condition can only be cleared with successful retesting by power cycle or MFR_RESET.

3Both bit 7 and bit 4 of STATUS_VOUT may also be set if a power stage UV or fault occurs during a true VOUT UV with the PWM still running. In this case

STATUS_IOUT and MFR_PADS will continue to accurately indicate power stage state, which does not require a full reset to clear.

4Detection of this condition must be enabled by setting bit 0 of MFR_PWM_MODE_LTC3888-1 (paged). No UV indication is given or response taken if bit

0 of MFR_PWM_MODE_LTC3888-1 is clear.

5MFR_PADS_LTC3888-1[15:14] respond to enabled power stage UV detection by indicating NOT READY (1’b0) for their respective channels, regardless

of PWM run state. Otherwise these bits indicate READY (1’b1).

6The exact nature of fault indicated in this case varies by manufacturer and can include such issues as gross output overcurrent or power stage

overtemperature.

LTM4677 Datasheet(PDF) 46 Page - Analog Devices

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