LTM4677 datasheet(69/110 Pages) AD

69 / 110 page

LTC3888-1

Rev. 0

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Two 470μF Panasonic 5mΩ POSCAPs and three 100μF

ceramic capacitors are chosen for each phase output to

maintain supply regulation during severe transient condi-

tions and to minimize output voltage ripple.

The loop compensation components C18, C21 (VOUT0)

and C19,C22 (VOUT1) provide a good starting point to

tune the crossover frequency by programming error

amplifer transconductance and internal RITH with the help

of LTpowerCAD, LTpowerPlay and built-in LTC3888-1 load

step emulation. With a 500kHz switching frequency, an

initial crossover target of 100kHz should provide good

transient performance. System phase margin of around

65° is recommended at that bandwidth.

For output current sensing, the TDA21470 provides a

voltage-mode monitor scaled to 5mV/A, ideal for the

LTC3888-1and allowing direct connection from IOUT to the

LTC3888-1 ISENSE pin. The IREF output of the LTC3888-1

is used to provide the necessary common mode refer-

ence to all power stages. Each DrMOS device then has

470nF of local bypassing on this DC reference (REFIN) to

limit introduction of switching noise and crosstalk. These

capacitors should be returned to GND (the LTC3888-1

package paddle) for best noise performance.

External temperatures of interest are also sensed by the

individual power stages. The highest temperature for each

rail is indicated on the shared TOUT/FLT bus, which is con-

nected directly to the respective LTC3888-1 TSNS input.

The required RSET resistor (18.7kΩ) is connected to GND.

Resistor configuration is then used on the ASEL0 and

ASEL1 pins to program PMBus address (MFR_ADDRESS)

to 0x28. Each LTC3888-1 must be configured for a

unique address. Using both ASEL pins to accomplish

this is recommended for simpliest in-system program-

ming. Check the selected address to avoid collision with

global addresses or other any other specific devices. The

LTC3888-1 also responds to 7-bit global addresses 0x5A

and 0x5B. MFR_ADDRESS and MFR_RAIL_ADDRESS

should not be set to either of these values. Resistors are

used to program ILIM0_CFG and ILIM1_CFG to set IOUT_

OC_WARN_LIMIT to 32A and IOUT_OC_FAULT_LIMIT

to 40A, based on the design value of 25A rated load

per phase (100A total) with a room temperature choke

saturation of 50A.

PMBus connection (three signals), as well as shared RUN

control and fault propagation (FAULT) for each rail are

provided. SYNC can be used to synchronize other PWMs

to this device if required.

Pull-ups are provided on all open-drain signals assuming

a maximum 100pF line load and PMBus rate of 100kHz.

These pins should not be left floating. Termination to

3.3V ensures the absolute maximum ratings for the pins

are not exceeded. All other operating parameters such

as soft-start/stop and desired fault responses are pro-

grammed via PMBus command values stored in internal

LTC3888-1 EEPROM.

APPLICATIONS INFORMATION

LTM4677 Datasheet(PDF) 69 Page - Analog Devices

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