LTM4677 datasheet(51/110 Pages) AD

51 / 110 page

LTC3888-1

Rev. 0

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driven on quickly. If the ratio of such a switched CLOAD

to COUT is greater than 1:50, the switch rise time should

be limited to approximately 25 • CLOAD. As an example, a

10μF switched load would require a 250μs rise time with

charging current limited to about 200mA.

PCB LAYOUT CONSIDERATIONS

To prevent magnetic and electrical field radiation, or high

frequency resonant problems, and to ensure correct IC

operation, proper layout of the components connected to

the LTC3888-1 is essential. Refer to Figure 29, which also

illustrates current waveforms typically present in the cir-

cuit branches. In this drawing SW0/1 and D0/1 respresent

salient features of the selected power stage. For maximum

efficiency, the switch node (input to L0/1) rise and fall

times should be minimized. The following PCB design

priority list will help ensure proper topology.

1. Place a ground or DC voltage layer between a power

layer and a small-signal layer. Generally, power planes

should be placed on the top layer (4-layer PCB), or top

and bottom layer if more than 4 layers are used. Use

wide/short copper traces for power components and

avoid improper use of thermal relief around power

plane vias to minimize resistance and inductance.

2. Low ESR input capacitors should be placed as close

as possible to the power stage FET supply and ground

connections with the shortest copper traces possible.

The power stage must be on the same layer of cop-

per as the input capacitors with a common topside

power connection at CIN. Do not attempt to split the

input decoupling for multiple phases, as a large reso-

nant loop can result. Vias should not be used to make

these connections. Avoid blocking forced air flow to

the power stages with large size passive components.

3. Place the inductor input as close as possible to the

power stage. Minimize the surface area of the switch

node. Make the trace width the minimum needed to

support the maximum output current. Avoid copper

fills or pours. Avoid running the connection on mul-

tiple copper layers in parallel. Minimize capacitance

from the switch node to any other trace or plane.

4. PCB traces for remote voltage sense should be run

together back to the LTC3888-1 in pairs with the small-

est spacing possible on any given layer on which they

are routed. Avoid high frequency switching signals

and ideally shield with ground planes. Locate any filter

component on these traces next to the LTC3888-1,

and not at the Kelvin sense location.

5. PCB traces for output current sense (ISENSE, IREF)

should avoid high frequency switching signals and

ideally be shielded with ground planes. Filter com-

ponents on these traces should return to GND (IC

paddle) and not to a local PGND.

6. Place low ESR output capacitors adjacent to the induc-

tor output and ground. Output capacitor ground con-

nections must feed into the same copper that con-

nects to the input capacitor ground before connecting

back to system ground.

7. Connection of switching ground to system ground,

small-signal analog ground or any internal ground

plane should be single-point. If the system has an

internal system ground plane, a good way to do this

is to cluster vias into a single star point to make the

connection. This cluster should be located directly

beneath the IC GND paddle, which serves as analog

signal ground. A useful CAD technique is to make

separate ground nets and use a 0Ω resistor to con-

nect them to system ground.

8. Place all small-signal components away from high

frequency switching nodes. Place decoupling capaci-

tors for the LTC3888-1 immediately adjacent to the IC.

9. A good rule of thumb for via count in a given high cur-

rent path is to use 0.5A per via. Be consistent when

applying this rule.

10. Copper fills or pours are good for all power connec-

tions except as noted above in rule 3. Copper planes

on multiple layers can also be used in parallel. This

helps with thermal management and lowers trace

inductance, which further improves EMI performance.

APPLICATIONS INFORMATION

LTM4677 Datasheet(PDF) 51 Page - Analog Devices

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