LTM4677 datasheet(59/110 Pages) AD

59 / 110 page

LTC3888-1

Rev. 0

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Load sharing accuracy is based on the power stage out-

put current monitor interface of each slave phase. The

gain matching errors of these channels tend to be small

and negligible. The input-referred offset of the LTC3888-1

current interface is trimmed at the factory but will still

dominate the sharing error budget, especially at lower

phase current levels. Specifications for on-chip and off-

chip output current matching are given in the Electrical

Characteristics table. These specifications do not include

the current error created by mismatch of the output cur-

rent monitors of the individual power stages.

Every master channel on a rail should use identical values

for all PMBus commands related to output voltage control

(including margin and start/stop timing), input and output

warning limits (both voltage and current), all fault limits

and associated responses, and all PWM configuration

controls. The correct current sense gain should also be

set for each master (IOUT_CAL_GAIN) to achieve accu-

rate IOUT telemetry and consistent fault handling across

phases.

A PolyPhase power supply significantly reduces the

amount of ripple current in both the input and output

capacitors. The RMS input ripple current is divided by,

and the effective ripple frequency is multiplied by, the

number of phases used as long as the input voltage is

greater than the number of phases times the output volt-

age. Output voltage ripple amplitude is also reduced by

the number of phases used. Figure 40 graphically illus-

trates the principle.

The worst-case RMS ripple current for a single stage

design peaks at an input voltage of twice the output volt-

age. The worst case RMS ripple current for a 2-phase

design peaks at output voltages of one-quarter and three-

quarters of the input voltage. When the RMS current is

calculated, higher effective duty factor results and the

peak current levels are divided as long as the current in

each stage is balanced. Refer to Application Note 19 for a

detailed description of how to calculate RMS current for a

single stage switching regulator. Figure 41 and Figure 42

illustrate how the input and output currents are reduced

by using an additional phase. For a 2-phase converter,

the input current peaks drop in half and the frequency is

doubled. The input capacitor requirement is then theoreti-

cally reduced by a factor of four.

APPLICATIONS INFORMATION

Figure 40. Single and 2-Phase Current Waveforms

388812 F40

SW1 V

ICIN

ICOUT

SINGLE PHASE

SW1 V

SW2 V

ICIN

IL2

IL1

ICOUT

DUAL PHASE

RIPPLE

Figure 41. Normalized RMS Input Ripple Current

0.1

0.2

0.3

0.4

388812 F41

0.5

0.6

DUTY FACTOR (VOUT/VIN)

0.1

0.3

0.5 0.6

0.2

0.4

0.7 0.8 0.9

1-PHASE

2-PHASE

DUTY FACTOR (VOUT/VIN)

0.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.3

0.5 0.6

388812 F42

0.2

0.4

0.7 0.8 0.9

1-PHASE

2-PHASE

Figure 42. Normalized Output Ripple Current

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