LTM4677 datasheet(57/110 Pages) AD

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LTC3888-1

Rev. 0

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As shown in Figure 38 master channel 0 and its assigned

slaves from the two ICs combine to form a single high

phase count rail with ideal phase separation, in this case

360/12 = 30 degrees. While a great deal of flexibility exists

in utilizing the remaining voltage control loops and slaves,

some phasing limitations do exist. For example, in a

10-phase case, the remaining three phases on each IC are

separated by 120 degrees, so a 2-phase rail built from one

of those loops would not be capable of 180° phasing. The

two remaining loops would also not produce uniform 60°

separation if combined into a single 6-phase rail. While

none of the phases on these remaining two 3-phase loops

overlap each other, one or more may overlap those of the

primary high count rail.

Whether using the phase expansion feature of the

LTC3888-1 or not, the following pins should be shared

between two or more devices devices on a large PolyPhase

rail:

• VIN (if separatre ICs)

• VSENSE± (see previous Output Voltage Sensing

discussion)

• ITH / ITHR

• TSNS/VDR_MON

• SYNC (if not using phase expansion)

• I2C bus pins (SCL, SDA)

• ALERT

• FAULT pins

• RUN

• SHARE_CLK (if separate ICs)

When ITH pins are shorted, one ITHR pin can be selected to

apply primary loop compensation, with all other ITHR pins

shorted to the common ITH. Alternatively, all ITHR pins can

be shorted, making the effective resistance the parallel

combination of all these RITH. This will reduce dynamic

range of RITH but will increase programming resolution.

Linear regulator outputs such as VDD33 and resistor config-

uration pins, including RSET, should not be shared between

devices. PGOOD may be shared between all master chan-

nels on a single rail, or a single PGOOD output can be

selected to indicate the rail output voltage is in regulation.

APPLICATIONS INFORMATION

All ICs of a PolyPhase rail may be required to share SYNC

pins. If phase expansion for a single rail is all that is

required, the IC providing the master clock simply drives

the clock slave IC SYNC input with its CLKOUT. If SYNC is

shared between ADI PSM devices, only one device should

be programmed to control the SYNC output. Refer to the

following section for additional PolyPhase details.

The PLL generates very accurate channel phase relation-

ships which can be selected with MFR_PWM_CONFIG_

LTC3888-1. For PolyPhase applications, all phases should

be spaced evenly around the unit circle for best results.

For instance, a 4-phase system should use a separation

of 90° between channels.

The PLL has a lock detection circuit. If the PLL should

lose lock during operation, bit 4 of the STATUS_MFR_

SPECIFIC command is asserted and the ALERT pin is

pulled low, if not masked. The fault can be cleared by

writing a 1 to STATUS_MFR_SPECIFIC bit 4.

POLYPHASE OPERATION AND LOAD SHARING

Single IC PolyPhase LTC3888-1 configuration are con-

trolled by bits [2:0] of MFR_PWM_CONFIG_LTC3888-1.

All necessary slave phase control is managed internal to

the device in this case. When operating a high power rail

requires between ten and sixteen phases, the LTC3888-1

affords dual-IC phase expansion to keep those phases ide-

ally spaced around the unit circle as shown in Figure 38.

To do this, bit 3 of MFR_PWM_CONFIG_LTC3888-1 is

set, making that device the clock master. The PGOOD0

pin is redefined to provide CLKOUT to drive the SYNC

input of the second LTC3888-1. A pull-up resistor to 3.3V

is still required on CLKOUT. Bits[2:0] of MFR_PWM_

CONFIG_LTC3888-1 are then set to the same value on

both ICs, yielding the following additional dual-IC rail

configurations:

• 10+(1 or 3)+(1 or 3)

• 12+(1 or 2)+(1 or 2)

• 14+1+1

• 16-phase

LTM4677 Datasheet(PDF) 57 Page - Analog Devices

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