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LTM4677 Datasheet(PDF) 66 Page - Analog Devices

Part # LTM4677
Description  Dual Loop 8-Phase Step-Down DC/DC Controller with Digital Power System Management
PDF  110 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

LTM4677 Datasheet(HTML) 66 Page - Analog Devices

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LTC3888-1
66
Rev. 0
For more information www.analog.com
APPLICATIONS INFORMATION
DC1613 or DC2086 will power the LTC3888-1 VDD33
supply, allowing in-circuit configuration or manufactur-
ing customization. With VDD33 applied in this fashion,
the device(s) can be initialized when the system is not
powered by using PMBus address 0x5B to send a value
of 0x2B to command 0xBD. If this is followed with a value
of 0xC4 to 0xBD at address 0x5B, the LTC3888-1 will
begin to communicate and allow PMBus command values
to be updated at its normal PMBus device address. Any
changes will become permanent (stored to EEPROM) by
a subsequent STORE_USER_ALL command. When VIN
is reapplied, MFR_RESET must be excuted to establish
normal operation if command 0xBD has been used for
communication in the absence of system power.
The DC1613 I2C connections are opto-isolated from
the host PC USB. The DC1613 3.3V current limit is only
100mA, so it should be used to power only one or two
LTC3888-1 devices in-system. Because of this limited
current sourcing capability, only the LTC3888-1 devices,
their associated pull-up resistors and the I2C pull-up
resistors should be powered from the isolated 3.3V sup-
ply provided by the DC1613. Using the DC2086 will enable
in-system programming of several tens of LTC3888-1
devices without normal system power applied. Some
small current, normally less than 1mA, may be driven
back into the internal INTVCC LDO output or VIN supply
by each LTC3888-1 when power is applied only to VDD33.
Any other device sharing the I2C bus with the LTC3888-1
should not have internal body diodes between SDA/SCL
pins and their respective logic supply, because this will
interfere with bus communication in the absence of sys-
tem power. Configure both masters to be off, for example
by driving both RUN pins low, to avoid providing power
to the load until the part is fully configured.
DESIGN EXAMPLE
As a design example, consider a 280W dual output appli-
cation such as the one shown in Figure 46, where VIN =
12V, VOUT0 = 1V, and VOUT1 = 1.8V. Both rails support
a rated load of 100A. The TDA21470 is chosen as the
power stage for both rails based on its output current
capability, feature set, and small package size. Assume
that an auxillary 5V supply VDR will be available in the
system for TDA21470 power requirements. Details are
shown in Figure 46 for biasing and bypassing one of the
power stages. This detail is not shown for the remaining
seven TDA21470 devices but should be repeated for each
(including VIN bypass and output filter capacitance), with
components located close to each device using the PCB
layout guidelines given in previous discussion.
The necessary local bypassing is then provided for the
LTC3888-1 INTVCC (4.7µF), VDD33 (2.2µF) and VDD25
(1µF) LDO outputs. These LDO outputs should not be
shared with outputs of other ICs that might have the same
name, because they have independent internal control
loops.
Next, the regulated output for each rail is established by
selecting suitable values for R284, R285 (VOUT1), R277
and R278 (VOUT0). Maintaining a total load on DAOUT of
50kΩ to 100kΩ is recommended.
The PWM_CONFIG pin is left open to select the factory
default master/slave configuration (4+4) and a PWM oper-
ating frequency (FREQUENCY_SWITCH) of 500kHz, both
of which are desired targets for this appliation. In this
configuration the four phases of each rail are separateed
by 90°, and none of the eight phases overlap, producing
the lowest input and output ripple possible.
The design will plan on a nominal output ripple of about
55% of IOUT to minimize the magnetics volume, and the
inductance value is chosen based on this assumption.
Each phase supplies an average of 25A to the output at
full load, resulting in a ripple of 14AP-P in each choke. A
215nH inductor would create this peak-to-peak ripple at
500kHz on the 1.8V rail. (Ripple on the 1V rail will be less.)
A Cooper FP1007R3-R22-R 220nH inductor is selected
with a 50A saturation current limit at room temperature.
For input filtering, a bank of six 270μF Panasonic OS_CON
capacitors are selected to provide acceptable AC imped-
ance against the designed converter ripple current. High
frequency bypassing (1Ω into 2.2μF) is provided for the
LTC3888-1 itself, and additional ceramic bulk bypass local
to each power stage will also lower ESR on this input at
higher frequencies.



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