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FXLS93421 Datasheet(PDF) 219 Page - NXP Semiconductors |
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FXLS93421 Datasheet(HTML) 219 Page - NXP Semiconductors |
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219 / 254 page  NXP Semiconductors FXLS9xxxx Dual channel inertial sensor 5. The master-receiver signals the end of the transfer to the slave transmitter. Following a Not Acknowledge bit, the master can transmit either a STOP to terminate the transfer, or a repeated START to initiate a new transfer. An example ACK and NACK are shown in Figure 101. aaa-030685 SDA ACK 9th clock pulse 9th clock pulse NACK SCL Figure 101. I2C acknowledge and not acknowledge transmission 15.5 I2C stop condition A bus operation is always terminated with a stop condition (STOP) from the master. A STOP is defined as a Low to high transition on SDA while SCL is high as shown in Figure 102. After the STOP has been transmitted by the master, the bus is considered free. Timing for the stop condition is specified in Section 10.14. aaa-030686 SDA STOP SCL Figure 102. I2C stop condition 15.6 I2C register transfers 15.6.1 Register write transfers The device supports I2C register write data transfers. Register write data transfers are constructed as follows: 1. The master transmits a START condition 2. The master transmits the 7-bit slave address 3. The master transmits a '0' for the Read/Write Bit to indicate a Write operation 4. The slave transmits an ACK 5. The master transmits the register address to be written 6. The slave transmits an ACK 7. The master transmits the data byte to be written to the register address FXLS9xxxx All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 6 — 8 February 2021 219 / 254 |
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